Ac Electrical Specifications Control Timing - Motorola MC68340 User Manual

11.6 AC ELECTRICAL SPECIFICATIONS CONTROL TIMING

(c), and (d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70 C; see numbered notes)
Num. Characteristic
System Frequency 1
Crystal Frequency
On-Chip VCO System Frequency
On-Chip VCO Frequency Range
External Clock Operation
PLL Start-up Time 2
Limp Mode Clock Frequency 3
SYNCR X-bit = 0
SYNCR X-bit = 1
CLKOUT stability 4
1 5
CLKOUT Period in Crystal Mode
1B 6
External Clock Input Period
1C 7
External Clock Input Period with PLL
2,3 8
CLKOUT Pulse Width in Crystal Mode
2B, 3B 9 CLKOUT Pulse Width in External Mode
CLKOUT Pulse Width in External w/PLL
2C,
Mode
3C 10
CLKOUT Rise and Fall Times
4,5
NOTES:
(a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V 0.3 V are preliminary
and apply only to the appropriate MC68340V low voltage part.
(b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V 5% operation.
(c) The 25.16 MHz @ 5.0 V 5% electrical specifications are preliminary.
(d) For extended temperature parts T A = –40 to +85 C. These specifications are preliminary.
1. All internal registers retain data at 0 Hz.
2. Assumes that a stable V CCSYN is applied, that an external filter capacitor with a value of 0.1 F is attached to
the XFC pin, and that the crystal oscillator is stable. Lock time is measured from power-up to RESET release.
This specification also applies to the period required for PLL lock after changing the W and Y frequency control
bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock
to lock after LPSTOP.
3. Determined by the initial control voltage applied to the on-chip VCO. The X-bit in the SYNCR controls a divide-
by-two scaler on the system clock output.
4. CLKOUT stability is the average deviation from programmed frequency measured at maximum f sys .
Measurement is made with a stable external clock input applied using the PLL.
5. All crystal mode clock specifications are based on using a 32.768-kHz crystal for the input.
6. When using the external clock input mode (MODCK reset value = 0 V), the minimum allowable t EXTcyc period
will be reduced when the duty cycle of the signal applied to EXTAL exceeds 5% tolerance. The relationship
between external clock input duty cycle and minimum t EXTcyc is expressed:
Minimum t EXTcyc period = minimum
Minimum external clock low and high times are based on a 45% duty cycle.
7. When using the external clock input mode with the PLL (MODCK reset value = 0 V), the external clock input duty
cycle can be at minimum 20% to produce a CLKOUT with a 50% duty cycle.
8. For crystal mode operation, the minimum CLKOUT pulse width is based on a 47% duty cycle.
9. For external clock mode operation, the minimum CLKOUT pulse width is based on a 45% duty cycle, with a 50%
duty cycle input clock.
11-6
Freescale Semiconductor, Inc.
Symbol
f sys
f XTAL
f sys
f VCO
f sys
t rc
f limp
CLK
t cyc
t EXTcyc
t EXTcyc
t CW
t EXTCW
t EXTCW
t Crf
/ (50% – external clock input duty cycle tolerance).
t EXTCW
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3.3 V 3.3 V or 5.0 V
8.39 MHz 16.78 MHz
Min Max Min Max
dc 8.39 dc 16.78
25 50 25 50
0.13 8.39 0.13 16.78
0.1 16.78 0.1 33.5
0 8 0 16
— 20 — 20
— f sys /2 — f sys /2
— f sys — f sys
–1 +1 –1 +1
119.2 — 59.6 —
125 — 62.5 —
125 — 62.5 —
56 — 28 —
56 — 28 —
62.5 — 31 —
— 10 — 5
(See notes (a), (b),
5.0 V
25.16 MHz
Min Max Unit
dc 25.16 MHz
25 50 kHz
0.13 25.16 MHz
0.1 50.3 MHz
0 25 MHz
— 20 ms
kHz
— f sys /2
— f sys
–1 +1 %
40 — ns
40 — ns
40 — ns
19 — ns
18 — ns
20 — ns
— 4 ns
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