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proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and
DSACK0 must remain negated throughout the asynchronous input setup and hold times
around the end of S2. If wait states are added, the MC68340 continues to sample
DSACK on the falling edges of the clock until one is recognized. The selected device
uses R/ W , DS , SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15–D8
and D7–D0. SIZ1/SIZ0 and A0 select the data bus sections. If it has not already done so,
the device asserts DSACK when it has successfully stored the data.
State 4—The MC68340 issues no new control signals during S4.
State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid
during S5 to provide address hold time for memory systems. R/ W and FC3–FC0 also
remain valid throughout S5. If more than one write cycle is required, states S0–S5 are
repeated for each write cycle. The external device keeps DSACK asserted until it detects
the negation of AS or DS (whichever it detects first). The device must remove its data and
negate DSACK within approximately one clock period after sensing the negation of AS
or DS .
3.4 CPU SPACE CYCLES
FC3–FC0 select user and supervisor program and data areas. The area selected by FC3–
FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP
broadcast, module base address register access, and interrupt acknowledge cycles
described in the following paragraphs use CPU space. The CPU space type, which is
encoded on A19–A16 during a CPU space operation, indicates the function that the
MC68340 is performing. On the MC68340, four of the encodings are implemented as
shown in Figure 3-10. All unused values are reserved by Motorola for additional CPU
space types.
FUNCTION
3
BREAKPOINT
0
ACKNOWLEDGE
3
LOW-POWER
0
STOP BROADCAST
3
MODULE BASE
0
ADDRESS
REGISTER ACCESS
3
INTERRUPT
0
ACKNOWLEDGE
MOTOROLA
Freescale Semiconductor, Inc.
CODE
0
31
1 1 1
0
0
0
0
0
0
0
0
0
31
1 1 1
0 0 0 0
0 0 0 0
31
0
1 1 1
0 0 0 0
0 0 0 0
0
31
1 1 1 1
1 1 1 1
1 1 1
Figure 3-10. CPU Space Address Encoding
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
CPU SPACE CYCLES
ADDRESS BUS
19
16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19
16
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
19
16
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
19
16
1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CPU SPACE
TYPE FIELD
0
BKPT#
T 0
0
0
0
LEVEL
1
3- 21
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