Autovector Interrupt Acknowledge Cycle; Interrupt Acknowledge Cycle Timing - Motorola MC68340 User Manual

S0
CLKOUT
A31–A4
A3–A1
A0
FC3–FC0
SIZ0
SIZ1
R/W
AS
DS
DSACKx
D7–D0
D15–D8
IRQ7–IRQ1
IACK7–IACK1
*Internal Arbitration may take between 0–2 clock cycles.
Figure 3-15. Interrupt Acknowledge Cycle Timing
3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting
device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting DSACK ,
the device asserts AVEC to terminate the cycle. If the DSACK
during an interrupt acknowledge cycle terminated by AVEC , the DSACK signals and
MOTOROLA
Freescale Semiconductor, Inc.
0–2 CLOCKS*
S2 S4 S0
VECTOR FROM 16-BIT PORT
READ
INTERNAL
CYCLE
ARBITRATION
MC68340 USER'S MANUAL
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S1 S2 S4
INTERRUPT LEVEL
CPU SPACE
1 BYTE
VECTOR FROM 8-BIT PORT
IACK CYCLE
S0 S2
WRITE
STACK
signals are asserted
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