Multidrop Mode Timing Diagram - Motorola MC68340 User Manual

Integrated processor with dma
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RxD
C1
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDYA
CS
STATUS DATA
OVERRUN
(SR4)
1
RTS
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1
2. Timing shown for OPCR(4) = 1 and MR1(6) = 0
3. R = Read
4. C = Received Character
N
A transmitted character from the master station consists of a start bit, a programmed
number of data bits, an address/data (A/D) bit flag, and a programmed number of stop
bits. The A/D bit identifies the type of character being transmitted to the slave station. The
character is interpreted as an address character if the A/D bit is set or as a data character
if the A/D bit is cleared. The polarity of the A/D bit is selected by programming bit 2 of the
MR1. The MR1 should be programmed before enabling the transmitter and loading the
corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream,
regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the
7-16
Freescale Semiconductor, Inc.
C2
C3
R
R
C1
Figure 7-8. Multidrop Mode Timing Diagram
MC68340 USER'S MANUAL
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Go to: www.freescale.com
C5
C6
C4
C6, C7, C8 ARE LOST
R
R
STATUS DATA
C2
C5
LOST
C8
C7
R R
R R
STATUS DATA
C3
C4
RESET BY COMMAND
MOTOROLA

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