Clock Selection Logic; Internal Control Logic; Timer Functional Diagram - Motorola MC68340 User Manual

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CLOCK
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8.1.1.4 CLOCK SELECTION LOGIC. The clock selection logic consists of two
multiplexers that select the clocks applied to the prescaler and counter. The first
multiplexer (labeled clock logic in Figure 8-2) selects between the clock input to the timer
(TINx) or one-half the frequency of the system clock (CLKOUT). This output of the first
multiplexer (called selected clock) is applied to both the 8-bit prescaler and the second
multiplexer. The second multiplexer selects the clock for the 16-bit counter, which is either
the selected clock or the 8-bit prescaler output.

8.1.2 Internal Control Logic

The timer receives operation commands on the IMB and, in turn, issues appropriate
operation signals to the internal timer control logic. This mechanism allows the timer
registers to be accessed and programmed. Refer to 8.4 Register Description for
additional information.
MOTOROLA
Freescale Semiconductor, Inc.
TIMER
MODULE CONFIGURATION REGISTER
INTERRUPT REGISTER
CONTROL REGISTER
STATUS REGISTER
PRELOAD 1 REGISTER
(SYSTEM CLOCK)
PRELOAD 2 REGISTER
16-BIT
MUX
COUNTER
COUNTER REGISTER
COMPARE REGISTER
Figure 8-2. Timer Functional Diagram
MC68340 USER'S MANUAL
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CLOCK
LOGIC
SELECTED
CLOCK
COUNTER
CLOCK
MUX
8-BIT
PRESCALER
TIMEOUT
16-BIT
COMPARATOR
EXTERNAL
INTERFACE
TIN
TGATE
TOUT
8- 3