Ccd Drive Clock Generator Circuit - Panasonic UF-6300 Service Manual

0V
OS
Shading Correction Circuit
The Shading Correction Circuit, included in IC30, is provided to correct for reduction in LED lamp
intensity around the optical lens and LED lamp intensity distortion due to shading of each bit. This circuit
scans the white reference on the transmitting document plate immediately before the document reaches
the scanning position and writes a compensation value according to the distortion of the waveform, at
the time, into the S-RAM (IC31).When the actual picture signal is input, the circuit corrects the picture
signal shading, according to this compensation value. This shading is carried out for each page during
transmission or copy.
Offset Control Circuit
The Offset Control Circuit consists of IC44, IC30 and IC28, and controls the black level of the CCD
output to be at 0V by using the input.
Picture Signal Binary Coding Correction Circuit
The Picture Signal Binary Coding Correction Circuit is included in IC30. It is used to obtain a binary
coding signal which is a corrected picture and error diffused signal of a false halftone signal, which is
detected from a shaded picture signal.
6.2.4

CCD Drive Clock Generator Circuit

This circuit is also contained in IC30. Its function is to generate FSG, FCK1, FCK2 clock signals, which are
required for driving the CCD. These clock signals are generated by the system clock generator circuit
derived from the 8 MHz clock signal that is input to IC30. Its timing chart is shown below. The FR signal is
input to the IC3 for synchronizing the IC30 and IC3.
CCD Output
IC28, 2
IC44
3V
0V
IC28, 1
R288
C175
R285
191
ABC Circuit Output
32
IC30
37
19
41
39
Control
Circuit
40