Generation Of Adc Timing Signal - Hitachi 902 Service Manual

(3) Reset Circuit
This board supervises the Vcc (+5 V) voltage with the power monitoring IC and generates
a reset sequence signal (ACFAIL/SYSRESET) for the main CPU at power on/off.
Approx. 4.8 V
Approx. 4.65 V
+5 V
ACFAIL
SYSRESET
(4)

Generation of ADC Timing Signal

The output from the photo-interrupter for ADC start set to the reaction disk is connected to
the ADC controller on the EMIO100 board via the delay circuit on this board.
For adjustment of the ADC timing, use the VR1 arranged at the front.
23 msec
270 msec
10 - 25
Approx. 4.8 V
Approx. 4.65 V
2 msec min.