Operation Of Clock Monitor - NEC 78K0 User Manual

19.4 Operation of Clock Monitor

This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows.
<Monitor start condition>
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1).
<Monitor stop condition>
• Reset is released and during the oscillation stabilization time
• In STOP mode and during the oscillation stabilization time
• When the X1 input clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation
stabilization time
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of main OSC control register (MOC)
MCC:
Table 19-2. Operation Status of Clock Monitor (When CLME = 1)
CPU Operation Clock
X1 input clock STOP mode
RESET input
Normal operation mode
HALT mode
Ring-OSC clock STOP mode
RESET input
Normal operation mode
HALT mode
Note The Ring-OSC clock is stopped only when the "Ring-OSC can be stopped by software" is selected by a
mask option. If "Ring-OSC cannot be stopped" is selected, the Ring-OSC clock cannot be stopped.
The clock monitor timing is as shown in Figure 19-3.
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CHAPTER 19 CLOCK MONITOR
Bit 7 of processor clock control register (PCC)
Operation Mode X1 Input Clock Status
Stopped
Oscillating
Stopped
Oscillating
Stopped
User's Manual U16227EJ2V0UD
Ring-OSC Clock Status Clock Monitor Status
Oscillating Stopped
Note
Stopped
Oscillating
Note
Stopped
Oscillating Operating
Note
Stopped Stopped
Oscillating Stopped
Operating
Stopped