NEC 78K0 User Manual page 482

Page
p.160 Revision of CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
p.178 Revision of CHAPTER 8 8-BIT TIMERS H0 AND H1
p.202 Modification of Figure 9-1 Watch Timer Block Diagram
p.208 Addition of Figure 9-4 Example of Generation of Watch Timer Interrupt Request (INTWT) (When
Interrupt Period = 0.5 s)
p.219 Revision of CHAPTER 11 A/D CONVERTER
p.240 Revision of CHAPTER 12 SERIAL INTERFACE UART0
p.261 Revision of CHAPTER 13 SERIAL INTERFACE UART6
p.299 Revision of CHAPTER 14 SERIAL INTERFACE CSI10
p.314 Addition of Note to INTLVI, POC, and LVI in Table 15-1 Interrupt Source List
p.317 Addition of Note 2 to Table 15-2 Flags Corresponding to Interrupt Request Sources
p.318 Addition of Caution 2 to Figure 15-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
p.321 Addition of Caution to Table 15-3 Ports Corresponding to EGPn and EGNn
p.326 Addition of software interrupt request item to Table 15-5 Relationship Between Interrupt Requests
Enabled for Multiple Interrupt Servicing During Interrupt Servicing
p.330 Modification of Figure 16-1 Block Diagram of Key Interrupt
p.332 Modification of Table 17-1 Relationship Between HALT Mode, STOP Mode, and Clock in old edition to
Table 17-1 Relationship Between Operation Clocks in Each Operation Status
p.334 Addition of Cautions 2 and 3 to Figure 17-1 Format of Oscillation Stabilization Time Counter Status
Register (OSTC)
p.336 Modification of Table 17-2 Operating Statuses in HALT Mode
p.340 Addition of (3) When subsystem clock is used as CPU clock to Figure 17-4 HALT Mode Release by
RESET Input
p.341 Modification of the following items in Table 17-4 Operating Statuses in STOP Mode
• 8-bit timer H0
• Serial interfaces UART0 and UART6
pp.346 to 348 Modification of Figure 18-1 Block Diagram of Reset Function to Figure 18-4 Timing of Reset in STOP
Mode by RESET Input
p.352 Modification of Figure 19-1 Block Diagram of Clock Monitor
p.354 Addition of normal operation mode to Table 19-2 Operation Status of Clock Monitor (When CLME = 1)
pp.357, 358 Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7)
Clock monitor status after Ring-OSC clock oscillation is stopped by software to Figure 19-3 Timing of
Clock Monitor
p.359 Addition of Note to description in 20.1 Functions of Power-on-Clear Circuit
p.360 Modification of Figure 20-1 Block Diagram of Power-on-Clear Circuit
p.363 Addition of Note to description in 21.1 Functions of Low-Voltage Detector
p.363 Modification of Figure 21-1 Block Diagram of Low-Voltage Detector
p.365 Modification of Note 5 in Figure 21-2 Format of Low-Voltage Detection Register (LVIM)
p.366 Addition of Note 2 and Caution to Figure 21-3 Format of Low-Voltage Detection Level Selection
Register (LVIS)
Modification of Figure 21-4 Timing of Low-Voltage Detector Internal Reset Signal Generation and
pp.368, 370
Figure 21-5 Timing of Low-Voltage Detector Interrupt Signal Generation
p.374 Partial modification of description of (2) When used as interrupt under <Action> in 21.5 Cautions for
Low-Voltage Detector
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APPENDIX D REVISION HISTORY
Description
User's Manual U16227EJ2V0UD
(2/3)