NEC 78K0 User Manual page 225

(3) A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in
ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion
result, and FF08H indicates the lower 2 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
RESET input makes ADCR undefined.
Figure 11-5. Format of A/D Conversion Result Register (ADCR)
Address: FF08H, FF09H
Symbol
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined.
conversion result following conversion completion before writing to ADM and ADS. Using
timing other than the above may cause an incorrect conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see
CHAPTER 30 CAUTIONS FOR WAIT.
CHAPTER 11 A/D CONVERTER
After reset: Undefined R
FF09H
User's Manual U16227EJ2V0UD
FF08H
0 0 0 0 0 0
Read the
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