NEC 78K0 User Manual page 272

(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Address: FF56H After reset: 00H R/W
Symbol 7
CKSR6 0
TPS63
0
0
0
0
0
0
0
0
1
1
1
1
Note To select the output of TM50 as the base clock, start the operation by setting 8-bit timer/event counter 50 so
that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then
set TPS63, TPS62, TPS61, and TPS60 to 1, 0, 1, and 1, respectively. It is not necessary to enable the
TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1).
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-
OSC clock, the operation of serial interface UART6 is not guaranteed.
2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. Figures in parentheses are for operation with f
2. f : X1 input clock oscillation frequency
X
272
CHAPTER 13 SERIAL INTERFACE UART6
Figure 13-8. Format of Clock Selection Register 6 (CKSR6)
6 5
0 0
TPS62 TPS61
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
Other than above
User's Manual U16227EJ2V0UD
4 3
0 TPS63 TPS62
TPS60 Base clock (f
0 f (10 MHz)
X
1 f /2 (5 MHz)
X
2
0 f /2 (2.5 MHz)
X
3
1 f /2 (1.25 MHz)
X
4
0 f /2 (625 kHz)
X
5
1 f /2 (312.5 kHz)
X
6
0 f /2 (156.25 kHz)
X
7
1 f /2 (78.13 kHz)
X
8
0 f /2 (39.06 kHz)
X
9
1 f /2 (19.53 kHz)
X
10
0 f /2 (9.77 kHz)
X
Note
1 TM50 output
Setting prohibited
= 10 MHz.
X
2 1 0
TPS61 TPS60
) selection
XCLK6