NEC 78K0 User Manual page 302

(2) Serial clock selection register 10 (CSIC10)
CSIC10 is used to specify the timing of the data transmission/reception and set the serial clock.
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 14-3. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol 7
CSIC10 0
CKP10
0
0
1
1
CKS102
0
0
0
0
1
1
1
1
Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the Ring-
OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial
interface CSI10 is not guaranteed.
2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
3. Clear CKP10 to 0 to use P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 as general-purpose
port pins.
4. The phase type of the data clock is type 1 after reset.
Remarks 1. Figures in parentheses are for operation with f
2. f : X1 input clock oscillation frequency
X
302
CHAPTER 14 SERIAL INTERFACE CSI10
6 5
0 0 CKP10
DAP10 Specification of data transmission/reception timing
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
CKS101 CKS100
0 0 f /2 (5 MHz)
X
0 1 f /2
X
1 0 f /2
X
1 1 f /2
X
0 0 f /2
X
0 1 f /2
X
1 0 f /2
X
1 1 External clock input to SCK10
User's Manual U16227EJ2V0UD
4 3
DAP10 CKS102
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI10 serial clock selection
2
(2.5 MHz)
3
(1.25 MHz)
4
(625 kHz)
5
(312.5 kHz)
6
(156.25 kHz)
7
(78.13 kHz)
= 10 MHz.
X
2 1 0
CKS101 CKS100
Type
1
2
3
4
Mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode