NEC 78K0 User Manual page 247

(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
Figure 12-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol 7
BRGC0 TPS01
TPS01
0
0
1
1
MDL04
0
0
0
0
•
•
•
•
•
1
1
1
1
1
Note To select the TM50 output as the base clock, start an operation by setting 8-bit timer/event counter 50 so
that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then
clear TPS01 and TPS00 to 0. It is not necessary to enable the TO50 pin as a timer output pin (bit 0
(TOE50) of the TMC register may be 0 or 1).
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-
OSC clock, the operation of serial interface UART0 is not guaranteed.
2. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
3. The baud rate value is the output clock of the 5-bit counter divided by 2.
CHAPTER 12 SERIAL INTERFACE UART0
6 5
TPS00 0 MDL04
TPS00
Note
0 TM50 output
1 f /2 (5 MHz)
X
3
0 f /2 (1.25 MHz)
X
5
1 f /2 (312.5 kHz)
X
MDL03 MDL02 MDL01
×
0
1 0
1 0
1 0
• •
• •
• •
• •
• •
1 0
1 0
1 1
1 1
1 1
User's Manual U16227EJ2V0UD
4 3 2
MDL03 MDL02
Base clock (f ) selection
XCLK0
MDL00 k
× × ×
Setting prohibited
0 0 8 f
XCLK0
0 1 9 f
XCLK0
1 0 10 f
XCLK0
• • •
• • •
• • •
• • •
• • •
1 0 26 f
XCLK0
1 1 27 f
XCLK0
0 0 28 f
XCLK0
1 0 30 f
XCLK0
1 1 31 f
XCLK0
1 0
MDL01 MDL00
Selection of 5-bit counter
output clock
/8
/9
/10
•
•
•
•
•
/26
/27
/28
/30
/31
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