Mitsubishi Electric MELSEC iQ-R Series User Manual page 525

■Error completion (receive wait timeout error)
CPU
Execute dedicated instruction
module
(G(P).CPRTCL)
Completion device
Status display device
at completion
C24
Target device
• When variables are included in receive packet elements, variable parts are not verified.
• When more than one receive packet is specified, received data is verified with the receive packet
information of the first registered packet in the order of registration. The receive processing is performed
once received data match one of the receive packet number, and further verification is not performed.
• The receive packet number which is matched as the result of the verification is stored in the control data of
the dedicated instruction (CPRTCL instruction).
(Receive
buffer clear)
* Only if it is specified
t: Reception waiting time
Verification mismatch
Receive packet
Appendix 5 Operation Image and Data Structure of Predefined Protocol
Error occurred
ON at error completion
Receive packet
APPENDICES APPENDIX
A
523