Mitsubishi Electric MELSEC iQ-R Series User Manual page 501

Address Purpose
Dec (Hex)
CH1 CH2
128 For
(80H) programmable
controller CPU
information clear
129 to 143 Use prohibited
(81H to 8FH)
144 304 For designation
(90H) (130H) of mode
switching
145 305 For designation
(91H) (131H) of mode
switching
146 306 Signal
(92H) (132H) specification
Name
Programmable controller CPU information clear
request
0: No request
4C43H: Requested
System area
Switching mode No. designation (0001H to
0007H, 0009H, 00FFH)
0000H: Match the setting in MELSOFT.
0001H: MC protocol (Format 1)
0002H: MC protocol (Format 2)
0003H: MC protocol (Format 3)
0004H: MC protocol (Format 4)
0005H: MC protocol (Format 5)
0006H: Nonprocedural protocol
0007H: Bidirectional protocol
0009H: Predefined protocol
00FFH: MELSOFT connection
Transmission specifications after switching
designation
Designates transmission specifications after
switching when b15 of this area is 1 (ON).
• Operation setting (b0)
0: Independent 1: Interlink
• Data bit (b1)
0: 7 bits 1: 8 bits
• Parity bit (b2)
0: None 1: Yes
• Odd/even parity (b3)
0: Odd 1: Even
• Stop bit (b4)
0: 1 bit 1: 2 bits
• Sum check code (b5)
0: None 1: Yes
• Online change (b6)
0: Disable 1: Enable
• Setting change (b7)
0: Disable 1: Enable
• Communication speed (b8 to b11)
1200 bps to 230400 bps
• For system (b12 to b14)
All 0
• Transmission specifications direction after
switching (b15)
0: Match settings in MELSOFT
1: Match settings in this area
RS and DTR signal status designation
0: OFF 1: ON
RS (RTS) signal (b0)
ER (DTR) signal (b2)
For system (b1), (b3) to (b15)
Defaul Protocol
t value
MC Non Bi Pd

0 RW

0 RW
0
5H
APPENDICES APPENDIX
Appendix 3 Buffer Memory
Reference
Page 455 How to
Clear Programmable
Controller CPU
Information
Page 380 I/O Signals
for Handshake with
CPU Module and
Buffer Memory
A
MELSEC iQ-R Serial
Communication
Module User's
Manual (Startup)
499