Kenwood TK-5810 Service Manual page 30

TK-5810 BG
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6. Control Circuit
The control circuit consists of the ASIC (IC708) and its
peripheral circuits. IC708 performs the following;
1) Switching between transmission and reception by PTT
signal input.
2) Reading system, zone, frequency, and program data
from the memory circuit.
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the DC voltage from the
squelch circuit.
5) Controlling the audio mute circuit by decode data input.
6-1. ASIC
The ASIC (IC708) is 32bit RISC processor, equipped with
peripheral function and ADC/DAC.
This CPU operates at 18.432MHz clock and 3.3V/1.5V
DC. It controls the fl ash memory, SRAM, DSP, the receive
circuit, the transmitter circuit, the control circuit, and trans-
fers data to or from an external device.
6-2. Memory Circuit
Memory circuit consists of the ASIC (IC708) and the
SRAM (IC703), the fl ash memory (IC700). The fl ash memo-
ry has capacity of 64M-bit that contains the transceiver con-
trol program for the ASIC and stores the data. It also stores
the data for transceiver channels and operating parameter
that are written by the FPU. This program can be easily
written from external devices. The SRAM has capacity of
2M-bit that contains work area and data area.
■ Flash memory
The fl ash memory stores the data that is written by the
FPU (KPG-95DG), tuning data (Deviation, Squelch, etc.), and
firmware program (User mode, Test mode, Tuning mode,
etc.).
■ SRAM (static memory)
The SRAM has temporary data area and work area.
When the power supply is off, it is backed up by an inter-
nal secondary lithium battery. Therefore, the save data does
not break.
■ Real-time clock
The clock function is based on real-time clock IC (IC704).
When the power supply is off, it is backed up by an internal
secondary lithium battery.
6-3. Display Unit (KCH-14/15/16)
The display unit is composed of the CPU and the LCD &
Key backlight etc.
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/5810H BG
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CIRCUIT DESCRIPTION
6-4. Temperature Detection Circuit
The temperature detection circuit detects the tempera-
ture using a temperature IC (IC702) and corrects the thermal
characteristic change of the receiver and transmitter adjust-
ments.
6-5. DSP
The DSP circuit consists of a DSP (IC701) and processes
the base band signal. The DSP operates on an external
clock of 18.432MHz (the same as the IC708), the I/O sec-
tion operates at 3.3V and the core section operates at 1.5V.
The DSP carries out the following processes:
• 4Level FSK processing
• Analog FM pre-emphasis/de-emphasis
• Vocoder processing between audio codec and modula-
tion/demodulation
• CAI processing, such as error correction encoding
• QT/DQT encoding/decoding
• DTMF/2tone/MSK encoding/decoding
• Compressor/expander processing
• Transmit/receive audio fi ltering processing
• Microphone amplifi er AGC processing
• Audio mute processing
• Modulation level processing
7. Power Supply Circuit
+B is connected to Final amplifi er and DC/DC converter
IC (IC4). IC4 regulates +B voltage to 5.0V (5M). 5M oper-
ates whenever +B is supplied. IC2 (33M), IC7 (33A) and IC8
(15M) are enabled while the 5M are operating. 33M, 33A
and 15M provide the power to CPU, DSP, and Flash memo-
ry. At this time CPU starts working.
Voltage detector IC (IC1) watches +B voltage. If +B volt-
age is higher than 8.6V, IC1 (/BINT) outputs High. If the /
BINT signal is high, Q3 (SB SW) is turned on by SBC signal
from CPU (High: SB=ON, Low: SB=OFF). When the SB is
turned on, IC5 (8C), IC3 (5C), IC9 (33GPS) start working. Q5
and Q10 and Q11 are controlled by SBC signal. If the SBC
signal becomes High, Q5 (33M2) operates and Q10 (33AC)
operates and Q11 (5MC SW) are turned on.
The CPU controls 8TC to High during transmission to
supply power (8T) for transmission circuit. The CPU con-
trols 8RC to High during reception to supply power (8R) for
reception circuit. When the CPU detects the PSW (Power
switch) signal, IGN (Ignition sense) signal or /BINT signal, it
controls the SBC signal to Low, and turns the transceiver
power (SB) off. When D1 and Q1 detect over-voltage condi-
tion, they turns Q3 (SB SW) off. But the CPU still works.
If +B is not provided to the transceiver, the power is pro-
vided to SRAM and RTC through the secondary battery con-
nected with CN4.