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No. 2D730-148E*O
(e)
T/R switch
The T/R switch is used to switch the impedance
of the echo signal channel between
the transmit event and the receive event.
During the receive event, this switch short-circuits the secondary transformer
to
provide a low echo signal channel impedance.
(f)
Address decoder (EPLD) and TC bus
The address decoder uses digital control lines to perform the required control for the
TR board. The address decoder serves as the "brains" of the TR board and
communicates
with the RC board via the TC bus.
The TC bus serves as a bidirectional interface with the RC board. This bus is the
digital communication
hub for the TR board, which is used to access the memory in
the TR address decoder, ID EEPROM, and TXPGs. The TC bus is comprised of two
data buses and one address bus. The data bits are broken down into two 16-bit
buses, TCOD[15:0] and TCI D[15:0], where each data bus is then connected to two
TXPGs. TCOD[15:0] is sent to TXPG ASIC 0, TXPG ASIC 2, and the ID EEPROM,
while TCI D[15:0] is sent to TXPG ASIC 1 and TXPG ASIC 3.
(g)
Reception resonance
Reception resonance has been achieved by inputting inductance into echo signal
lines in parallel.
A coil is connected between the echo signal line and GND. There are four other
inductance coils that can be selected.
The resonance can be changed by using
these inductance coils in various combinations.
(h)
Fault detection and protection circuit
The TR board generates two types of interrupts:
transmission
interrupts and clock
detection interrupts.
a.
Transmission
interrupt
A transmission
interrupt is generated
when TXENO and TXENI are both "H"
simultaneously.
This occurs only if there is a hardware fault or if the address
decoder test bit is set. The address decoder EPLD always monitors the TXENO
and TXENI lines and sets the interrupt status bit when it senses that both signals
become "H" simultaneously.
When this bit is set, the TR board stops
transmission
by making TXENO and TXEN 1 "L" and transfers the transmission
inhibit signal and the interrupt signal to the system simultaneously
to indicate that
a system malfunction
has occurred.
This disables transmission
to all three TR
boards, not just the TR board where the error occurred.
b.
Clock detection interrupt
A clock detection interrupt is generated when the PECL clock in the front-end unit
stops before the TXPG completes transmission
and the transmission
for all three
TR boards stops. This is extremely dangerous for the TR board because it
leaves the TXPG output signals which drive the FET of the transmission
circuit in
an unknown state. If the TXPG output signals are fixed to "H", the FET of the
transmission
circuit may be broken.
4-10
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