Table of Contents
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No. 2D730-148E*O
(e)
Inter-face
1) CB address decoder (EPLD)
The CB address decoder (EPLD) decodes data from the TC bus and generates
all the control signals required for the TXPG, ID EEPROM interfacing, control of
buffer direction, and CB board. The TC bus is a bidirectional bus and consists of
an 18-bit address, 16-bit data, an enable signal, and a handshaking
signal.
2)
PECL clocks
The clocks for the CB board are derived from the PECL clock (four-phase,
40
MHz) RCFECK [0:3] output from the RC and the sync signal RCFECKE.
The PECL clock is used in the TXPG. The clock converted from RCFECKO and
RCFECK2 to TLL is used in the CB board.
3)
ID EEPROM
The ID EEPROM stores information
related to the serial number, hardware
revision, firmware revision, board ID, and drawing number.
This device also
stores the IQ calibration data that is used to correct the gain and phase
differences
between the in-phase and quadrature-phase
circuits in the
quadrature
demodulator
(quadrature
demodulator
circuit) on the BE board.
The capacity is 8 k x 8 bits and this device is accessed via the CB address
decoder EPLD and the TC bus.
4-20
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