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No. 2D730-148E*O
4.2.1
BE
(1)
Outline
The BE board consists of the following blocks and performs data processing in all image
modes after performing phasing/addition.
l
DR (Digital Receiver)
l
EP (Echo Processor)
l
FP (Flow Processor)
l
SIP (Signal & Image Processor)
l
SC (Scan Converter)
l
PCI I/F
The features of the architecture of this board are the miniaturization
of circuits using an
ASIC with a high level of integration and the provision of a buffer memory for each block to
enable independent
data processing.
(2)
Functions
The composition and functions of each block in the BE board are described below.
(4
DR
This consists of four DR-ASICs for quad signal processing (QSP). The following
functions are performed in all modes.
l
DC filtering
Removes the DC components.
l
Digital TGC (time gain control)
Controls the STC.
l
Baseband conversion
Performs orthogonal detection depending
on the reception center frequency data
and converts the frequency to the baseband signal to obtain real and imaginary
signals.
l
Decimation filter
Performs decimation for input data with 1024 samples or less per vector.
l
Dynamic filter
Sets the LPF to the echo signal depending
on depth.
In addition to the functions shown above, the following function is also performed
in
the PWD mode.
l
Range gating
Range gating integration is performed for the sample volume.
4-24
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