Mitsubishi Electric MELSEC iQ-R Series User Manual page 221

Time synchronization
■ Time distribution interval setting of the CPU module (Un\G1275136)
The time distribution interval of the CPU module on the master station to device stations is set (CPU No.1 when the multiple
CPU system is used). This setting is set to the buffer memory of the master station.
When the setting is changed, the new setting value is enabled after the interval of the distribution operating with the old setting
value has elapsed. The setting value is distributed once after the distribution interval elapses. If the new setting value needs to
be enabled immediately, stop the distribution and set the value.
• 0000H: 10 s
• 0001H to FFFEH: (Send using the set time interval (second))
• FFFFH: (Distribution stop)
(Default: 0000H)
Grandmaster information
The grandmaster status of the own station and MAC address are stored.
■ Grandmaster (Un\G1275904)
When the own station is the grandmaster, "1" is stored.
• 1: Own station is the grandmaster
• 0: Another station is the grandmaster
■ Grandmaster MAC address (Un\G1275907 to Un\G1275909)
The grandmaster MAC address is stored.
• Un\G1275907: 5th byte, 6th byte of the MAC address
• Un\G1275908: 3rd byte, 4th byte of the MAC address
• Un\G1275909: 1st byte, 2nd byte of the MAC address
Time synchronization setting
■ PTP frame send source check enable/disable (Un\G1275933)
• 1: Check
• 0: Do not check
■ PTP frame send source check result (P1) (Un\G1275934)
• 1: Two or more send sources
• 0: One send source
■ PTP frame send source check result (P2) (Un\G1275935)
• 1: Two or more send sources
• 0: One send source
Appendix 1 Buffer Memory (When Using the PLCopen Motion Control FB Mode)
A
APPX
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