Mitsubishi Electric MELSEC Q Series User Manual page 255

(1) Accessibility
Accessibility of the CPU shared memory is illustrated below.
Power supply
CPU shared
memory
Area name
area
*1
address
0 (0 )
H H
to
1FF (5F )
H H
200 (60 ) QCPU
H H
to standard
7FF (BF ) area
H H
800 (C0 )
H H
to
FFF (1FF )
H H
1000
H
to Use prohibited*3
270F
H
2710
H
Multiple CPU high speed
to
transmission area
5F0F
H
*1 : When CPU No.1 is a Basic model QCPU, addresses of the CPU shared memory are as shown in parentheses.
*2 : For information on how to access from another CPU (programmable controller CPU or Motion CPU), refer to the manual for each
CPU module.
*3 : Q00UCPU, Q01UCPU, and Q02UCPU have no unavailable area or multiple CPU high speed transmission area.
Programmable Programmable controller CPU
controller CPU Motion CPU
C Controller
module (other)
2)
Shared CPU memory Shared CPU memory
for other modules for other modules
Program
Sequence
program
1) Access to host
CPU
Write
Host CPU
operation 
information area
System area

Auto refresh area

User setting area



*3
CHAPTER 14 FUNCTIONS USED BY MULTIPLE CPU SYSTEM
C Controller
module (host)
User program
2) 1)
Shared CPU memory
for the host module
1) Access to host CPU
2) Access to another CPU
3)
3) Access to host CPU
Access from host CPU
2) Access to another
CPU
Read Write Read
 
 
 
 
 
 
Access from another
*2
CPU
3) Access to host CPU
Write Read
  
  
  
  
  
  
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