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Section 11
Testing functionality by secondary injection
6.
Vary the faulty phase voltage to achieve the impedance at the test point P2. At this point,
observe that the output ZOUT is activated and then continue to inject for a duration greater
than tP1.
7.
Inject the faulty phase voltage to achieve the impedance at the test point P3. At this point,
observe that the outputs ZIN and START are activated. It indicates that power swing has been
detected.
8.
Inject the faulty phase voltage in accordance with the test point P1.
9.
At this condition, the outputs ZIN and ZOUT get deactivated and START signal will be
maintained for a set duration of tH.
10.
To detect consecutive power swings, repeat steps 5, 6,
START will be activated.
11.
Repeat step
12.
Repeat step
13.
At this condition, it will be detected as consecutive power swing and the output signal START
will be maintained.
14.
Repeat step
disappear after set duration of tH from the instance of step 13.
15.
Repeat the above steps to test and detect power swing condition in at least two phases by
enabling input REL2PH.
16.
By enabling the input BLK1PH, operation mode for power swing detection in any phase will be
blocked.
17.
Similarly, operation mode for power swing detection in at least two phases will be blocked by
enabling the input BLK2PH.
18.
Repeat steps 5,
START, ZOUT and ZIN will be deactivated.
19.
Output signal START will also get activated instantaneously by enabling input EXTERNAL and
this input signal can be configured in ACT to the output derived from some external logics used
to detect power swings. By enabling the input signal BLOCK, the output signal START will be
deactivated.
Testing the inhibit logic of power swing detection function
The following output signals shall be configured to binary output available: ZOUT, measured
impedance within outer impedance boundary and ZIN, measured impedance within inner impedance
boundary and START, power swing detection.
1.
Set X1InFw, R1LIn, X1InRv, R1FInFw, R1FInRv, ArgLd, RLdOutFw, RLdOutRv, kLdRFw and
kLdRRv to values that are in accordance with the selectivity plan and the corresponding
operating characteristic is shown in Figure 40.
2.
Set OperationLdCh to On and set timers tP1, tP2, tW, tH, tR1, tR2 and tEF to their default
values.
3.
Enable the input signal REL1PH to detect the power swing in one of the three phases.
Inhibit START output by the presence of residual current
Preconditions
The input signal I0CHECK, residual current (3I0) detection used to inhibit the start output, must be
configured to the output signal STPE on the FDPSPDIS, FRPSPDIS, ZMFPDIS or ZMFCPDIS
function.
The input signal BLKI02, block inhibit of the start output for subsequent residual current detection, is
connected to FALSE.
1.
Create a test sequence such that power swing has been detected, which can be done by
referring to steps 5, 6 and 7 described in section
ZMBURPSB
all three phases. With this condition, the output signal START will be activated.
2.
Create a condition such that residual current is measured (that is, earth fault occurs in the
power system) and its value should be above the value seen during unbalanced loading
130
6
and inject before the expiration of timer tW. The output ZOUT will be activated.
7
after a set duration of tP2. The output ZIN will be activated.
8
and the outputs ZOUT and ZIN get deactivated. The output signal START will
6
and 7, and enable the input signal BLOCK. At this condition, the outputs
and inject voltage in one of the phases accordingly by keeping constant current in
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7
and 8. With this condition, the output
GUID-1E0D044A-89F5-4382-B78E-0927E271C54E v1
GUID-B1AFF8D6-FD37-47AA-84A4-DD98E920CCA7 v1
Testing the power swing detection logic
Transformer protection RET670
1MRK 504 165-UEN Rev. K
Commissioning manual
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