Completing The Test; Four Step Residual Overcurrent Protection, (Zero Sequence Or Negative Sequence Directionality) Ef4Ptoc; Function Revision History; Four Step Directional Earth Fault Protection - Hitachi RET670 Commissioning Manual

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Section 11
Testing functionality by secondary injection
11.5.3.2

Completing the test

Continue to test another function or end the test by changing the TESTMODE setting to Off. Restore
connections and settings to the original values, if changed for testing purposes.
11.5.4
Four step residual overcurrent protection, (Zero sequence or
negative sequence directionality) EF4PTOC
Prepare the IED for verification of settings outlined in Section
Values of the logical signals for D2PTOC are available on the local HMI under Main menu/Test/
Function status /Current protection/ResidualOverCurr4Step(51N_67N,4(IN>)) /
EF4PTOC(51N_67N;4(IN>)):x, where x = instance number.
The Signal Monitoring in PCM600 shows the same signals that are available on the local HMI.
11.5.4.1

Function revision history

Document
revision
A
B
C
D
E
F
G
H
J
11.5.4.2

Four step directional earth fault protection

1.
Connect the test set for single current injection to the appropriate IED terminals.
Connect the injection current to terminals L1 and neutral.
2.
Set the injected polarizing voltage slightly larger than the set minimum polarizing voltage (5% of
Ur) and set the injection current to lag the voltage by an angle equal to the set reference
characteristic angle (AngleRCA), if the forward directional function is selected.
If reverse directional function is selected, set the injection current to lag the polarizing voltage
by an angle equal to RCA+ 180°.
3.
Increase the injected current and note the value at which the studied step of the function
operates.
4.
Decrease the current slowly and note the reset value.
5.
If the test has been performed by injection of current in phase L1, repeat the test, injecting
current into terminals L2 and L3 with a polarizing voltage connected to terminals L2,
respectively L3.
6.
Block lower set steps when testing higher set steps according to the instructions that follow.
7.
Connect a trip output contact to a timer.
162
Product
History
revision
2.2.1
-
2.2.1
-
2.2.2
Technical data table updated with note "Operate time and reset time are only valid if
harmonic blocking is turned off for a step".
2.2.3
-
2.2.3
-
2.2.4
-
2.2.4
-
2.2.4
The phase selection logic is added to allow phase segregated trip. The new phase
selections outputs added to this release are PHSELL1, PHSELL2 and PHSELL3. The
setting EnPhaseSel is added to enable or disable phase selection. The maximum value
changed to 2000.0 % of IBase for IMin1, IMin2, IMin3 and IMin4 settings.
2.2.5
The harmonic restrain function changed to freeze the definite and IDMT timers.
© 2017 - 2022 Hitachi Energy. All rights reserved
1MRK 504 165-UEN Rev. K
"Preparing the IED to verify
GUID-0F9199B0-3F86-45E0-AFC2-747052A20AE1 v2
Transformer protection RET670
Commissioning manual
SEMOD52967-24 v5
SEMOD53296-3 v10
settings".
SEMOD53296-208 v8

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