Hitachi RET670 Commissioning Manual page 217

1MRK 504 165-UEN Rev. K
Step no.
4-e**
4-f
4-g
4-h
- Steps 4–f, 4–g and 4–h can also be done phase wise.
* - UBase is considered as 400 kV and VT ratio as 400 kV/110 V
The voltage inputs U
phase L1.
** - This step should be done only during Factory Acceptance Test (FAT). At field, the testing should be
done with the stored field values.
To calculate PUDIFL1 in steps 4-f, 4-g and 4-h, use the following equations:
UDIFL
IECEQUATION19217 V1 EN-US
Transformer protection RET670
Commissioning manual
Changes after step 2
Activate binary input TRIGCOMP for 1 s
Inject U = 23.04 V in secondary at rated
TapL1
frequency
Repeat
Inject U = 22.31 V in secondary at rated
TapL1
frequency
Repeat
Inject U = 21.83 V in secondary at rated
TapL1
frequency
, U , and U
L1 L2 L3
1
  
1 U U
L 1 TapL
USEDURATL 1
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WARNING signal test
ALARM signal Test
Sub-step 4–a and Sub-step 4–b
TRIP Signal Test
Sub-step 4–a and Sub-step 4–b
refer to the bus voltages and U
1
Testing functionality by secondary injection
Expected output
• The output COMPEXED
should become HIGH for
100 ms and LASTCOMP
output should display the
date and time of
compensation
• URATIOL1 and
USEDURATL1 should
show 0.382
• DIFURATL1 should
become LOW
• WARNING and WRNL1
signals should become
HIGH after a time delay
given by the setting
tDefWrn
• PUDIFL1 should show 5.03
%
• ALARM and ALML1 signals
should become HIGH after
a time delay given by the
setting tDefAlm
• PUDIFL1 should show
8.04%
• STARTBFI_3P and STL1
signals should become
HIGH after a time delay
given by the setting
tDefTrip
• TRIP and TRL1 signals
should become HIGH, if
BlockTrip is set to Trip
enabled
• PUDIFL1 should show
10.01%
refers to the tap voltage of
TapL1
Section 11
(Equation 110)
211