Hitachi RET670 Commissioning Manual page 219

1MRK 504 165-UEN Rev. K
Step no.
4-g
4-h
4-i
- Steps 4–g, 4–h and 4–I can also be done phase wise.
* - UBase considered as 400 kV and VT ratio as 400kV/110V
The voltage inputs U
phase L1.
* * - This step should be done only during Factory Acceptance Test (FAT). At field, the testing should be
done with the stored field values.
To calculate PUDIFL1 in steps 4-g, 4-h and 4-i, use the following equations:
IECEQUATION19128 V1 EN-US
IECEQUATION19129 V1 EN-US
Verifying the function when neutral VT is unavailable
If the neutral VT is not available, then the setting NeutVoltMeas is set to Not available.
1. Set the following parameters:
•
•
•
•
•
•
Transformer protection RET670
Commissioning manual
Changes after step 2
Inject U
TapL1
rated frequency
Repeat step
Inject U
Tap1
rated frequency
Inject U
TapL1
frequency
, U , and U
L1 L2
1
 
  
UDIFL 1 U U
L 1 N
USEDURATL
UDIFL 1
= ´
PUDIFL 1 100
UBase 3
Operation =ON
tDefWrn =5 s; tDefAlm =5 s; tDefTrip =5 s
SCBGndType =Ungrounded
NeutVoltMeas =Not available
Udif> =10% UB
UdifAlm> =8% UB
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WARNING Signal Test
= 30.00 V in secondary at
ALARM Signal Test
Sub-step 4–a and Sub-step 4–b
= 29.00 V in secondary at
TRIP Signal Test
Repeat Sub-step 4–a and Sub-step 4–b
= 28 V in secondary at rated
refer to the bus voltages and U
L3
 
 
U U
TapL 1 N
1
Testing functionality by secondary injection
Expected output
• WARNING and WRNL1
signals should become HIGH
after a time delay given by the
setting tDefWrn
• PUDIFL1 should show 5.61 %
• ALARM and ALML1 signals
should become HIGH after a
time delay given by the setting
tDefAlm
• PUDIFL1 should show 8.81%
• START and STL1 signals
should become HIGH after a
time delay given by the setting
tDefTrip
• TRIP and TRL1 signals should
become HIGH, if BlockTrip is
set to Trip enabled
• PUDIFL1 should show 12.01%
refers to the tap voltage of
TapL1
GUID-56FBF2D2-74FF-4091-9B2B-14299F50670D v1
Section 11
(Equation 112)
(Equation 113)
213