Programmable Logic (Psl); Description Of P442 And P444 Logic Nodes; Sorted By Ddb Number - GE MiCOM P40 Agile Technical Manual

Programmable Logic
MiCOM 40 Agile P442, P444
1

PROGRAMMABLE LOGIC (PSL)

The Programmable Scheme Logic (PSL) is a module of programmable logic gates and
timers in the IED, which can be used to create customised internal logic. This is done by
combining the IED's digital inputs with internally generated digital signals using logic gates
and timers, then mapping the resultant signals to the IED's digital outputs and LEDs.
The Programmable Scheme Logic (PSL) Editor allows you to create and edit scheme logic
diagrams to suit your own particular application.
Further information is available in the Help system and in the Settings Application Software
Guide P40-M&CR-UG-EN-n, where n is the latest version of the settings application
software.
1.1

Description of P442 and P444 Logic Nodes

1.1.1

Sorted by DDB number

Ordinal English Text
Relay Label 01 to
0 to 63
Relay Label 64
64 Opto Label 01
65 Opto Label 02
66 to 95 Opto Label 03 to
Opto Label 32
96 to --
173
174 General Alarm
175 Prot'n Disabled
176 F out of Range
177 VT Fail Alarm
Description
OUTPUT RELAY 1 to
OUTPUT RELAY 64
High level when a DDB cell (linked by PSL logic) is at 1.
State depends on the logic set in the PSL (MiCOM S1
Agile)
These programmable relays are assigned in the default
PSL, with the following logic conditions (see section
1.8.2):
- Pulse time-delay
- Pick Up/Drop Off Time-delay
- Dwell Time-delay
- Pick Up Time-delay
- Drop Off Time-delay
- Latching
- Straight (used in default PSL)
OPTO ISOLATOR 1
Set to 1 when the opto input is energised for a minimum
time: 7 ms (48 Vdc), 10 ms (universal) to be validated by
internal logic
To enable the selection of a setting group by state
change of the opto isolated logic inputs 1 and 2,
disconnect Opto inputs 01 and 02 in the PSL (Opto
inputs 01 and 02 must not be connected to any output
signal)
OPTO ISOLATOR 2
Set to 1 when the opto input is energised for a minimum
time: 7 ms (48 Vdc), 10 ms (universal) to be validated by
internal logic
To enable the selection of a setting group by state
change of the opto isolated logic inputs 1 and 2,
disconnect Opto inputs 01 and 02 in the PSL (Opto
inputs 01 and 02 must not be connected to any output
signal)
OPTO ISOLATOR 3 to
OPTO ISOLATOR 32
Set to 1 when the opto input is energised for a minimum
time:7 ms (48 Vdc), 10 ms (universal) to be validated by
internal logic
Unused
Groupment of all alarms
Protection is disabled and test mode enabled
Frequency tracking does not work correctly (provides a
Frequency Out-of-Range indication)
Fuse failure indication (VT alarm). High when the opto
input is energised (copy of MCB) OR an internal Fuse
Failure is confirmed when the VTS timer elapses.
P44x/EN PL/Hb6
(PL) 6-5
Source
RELAY
OPTO
OPTO
OPTO
PSL (OUT)
PSL (OUT)
PSL (OUT)
PSL (OUT)
VT
Supervision