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7.2.1.2.2
bus integrity test
This is a test designed to induce a bit error in the dependence/independence of the
address bus and data bus using a large amount of consecutive data such as 1, 0, 1,
0, etc.
(1) Input format
For the bus integrity test, confirm whether to save the program on the flash
ROM.
If Y is selected, the programs in the flash ROM for the test are saved on the
SDRAM. After the bus integrity test is finished, they are written on the flash
ROM again.
Save programs from FlashROM? [Y/N] >
Start address? [0x00000000:default, -1:top]
End
address? [0x00FFFFFF:default, -1:bottom] >
The format for the address rage is the same as that for the data compare test.
(2) Test results
The test results are displayed as shown below.
Save programs from FlashROM? [Y/N] > Y
Start address? [0x00000000:default, -1:top]
End
address? [0x00FFFFFF:default, -1:bottom] > FFFFFF
Check FlashROM 0x00000000 - 0x00FFFFFF
save programs ... done.
write 0xAAAAAAAA/0x55555555 ... block 134
verify ... done.
FlashROM check done.
recover programs to FlashROM ... block 134
recover programs to FlashROM ... verify done.
Error messages
Same as the data compare test.
7.2.1.3
NIC test
This test confirms the operation of the local bus and the read/write function for data
for the Ethernet controller.
NIC test
---------------------
1: data compare test
2: bus integrity test
3: return
select >
>
Enter
> 0
Enter
Enter
SERVIS IP-Serial
1p Converter
User's Guide
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