Table of Contents
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Index
A
AC timings 2-7
Address Acknowledge signal 1-10
Address Bus Busy signal 1-9
Address Bus signal 1-8
Address Latch Enable (ALE) 1-16
Address Retry signal 1-10
applications iv
B
block diagram i
Boot Mode 0–1 (BTM[0–1]) signals 1-7
Buffer Control 0 (BCTL0) 1-16
Buffer Control 1 (BCTL1) 1-16
Burst Address 27–28 (BADDR[27–28]) 1-16
Burst Address 29 signal 1-9
Burst Address 30 signal 1-9
BUS DF 2-4
Bus Grant signal 1-9
Bus Output Enable signal 1-17
Bus Parity Byte Select signal 1-17
Bus Request signal 1-9
Bus SDRAM A10 signal 1-16
Bus SDRAM Address Multiplexer signal 1-17
Bus SDRAM CAS signal 1-17
Bus SDRAM RAS signal 1-17
Bus SDRAM Write Enable signal 1-16
Bus Transfer Start signal 1-10
Bus UPM General-Purpose Line 0 signal 1-16
Bus UPM General-Purpose Line 1 signal 1-16
Bus UPM General-Purpose Line 2 signal 1-17
Bus UPM General-Purpose Line 3 signal 1-17
Bus UPM General-Purpose Line 4 signal 1-17
Bus UPM General-Purpose Line 5 signal 1-17
Bus UPM Wait signal 1-17
Bus Write Enable (PWE[0–7]) 1-16
C
capabilities iv
Chip Select (CS0–7) 1-16
clock 1-5
clocks
Communications Processor Module (CPM) iii
JTAG 2-23
operation 2-8
System Clock Control Register (SCCR) 2-5
System Clock Mode Register (SCMR) 2-5
coprocessor iii
CPM inputs 2-20
D
Data Bus 1-11
Data Bus Bit 32–47 signals 1-10
Data Bus Bit 48–51 signals 1-10
Data Bus Bit 52 signal 1-11
Data Bus Bit 53 signal 1-11
Data Bus Bit 54 signal 1-11
Data Bus Bit 55 signal 1-11
Data Bus Bit 56 signal 1-12
Data Bus Bit 57 signal 1-12
Data Bus Bit 58 signal 1-12
Data Bus Bit 59 signal 1-12
Data Bus Bit 60 signal 1-12
Data Bus Bit 61–63 signals 1-12
Data Bus Busy signal 1-10
Data Bus Grant signal 1-10
Data Bus Most Significant Word (D[0–31]) 1-10
Data Parity 0 (DP0) 1-13
Data Parity 1 (DP1) 1-13
Data Parity 2 (DP2) 1-13
Data Parity 3 (DP3) 1-13
Data Parity 4 (DP4) 1-14
Data Parity 5 (DP5) 1-14
Data Parity 6 (DP6) 1-14
Data Parity 7 (DP7) 1-14
Data Valid (PSDVAL) 1-15
DC electrical characteristics 2-3
Debug Request (DBREQ) signal 1-6
design considerations
electrical 4-2
layout practices 4-4
power 4-2
power dissipation 4-3
thermal 4-1
DMA Acknowledge 3 (DACK3) 1-14
DMA Acknowledge 4(DACK4) 1-14
DMA controller iii
DMA Request 3 (DREQ3) 1-14
DMA Request 4 (DREQ4) 1-14
documentation iv
E
EE signals 2-22
electrical characteristics
DC 2-3
Index-1
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