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System Bus, HDI16, and Interrupt Signals
TS
AACK
ARTRY
DBG
DBB
IRQ3
D[0–31]
D[32–47]
HD[0–15]
D[48–51]
HA[0–3]
1-10
Table 1-4.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Input/Output
Bus Transfer Start
Signals the beginning of a new address bus tenure. The MSC8101 asserts this
signal when one of its internal bus masters (SC140 core or DMA) begins an
address tenure. When the MSC8101 senses this pin being asserted by an external
bus master, it responds to the address bus tenure as required (snoop if enabled,
access internal MSC8101 resources, memory controller support).
Input/Output
Address Acknowledge
A bus slave asserts this signal to indicate that it identified the address tenure.
Assertion of this signal terminates the address tenure.
Input
Address Retry
Assertion of this signal indicates that the bus transaction should be retried by the
bus master. The MSC8101 asserts this signal to enforce data coherency with its
internal cache and to prevent deadlock situations.
Input/Output
Data Bus Grant
Output
An output when an internal arbiter is used. The MSC8101 asserts this pin as an
output to grant data bus ownership to an external bus master.
Input
An input when an external arbiter is used. The external arbiter should assert this
pin as an input to grant data bus ownership to the MSC8101.
Input/Output
Data Bus Busy
Output
The MSC8101 asserts this pin as an output for the duration of the data bus tenure.
Following a TA, which terminates the data bus tenure, the MSC8101 deasserts
DBB for a fraction of a bus cycle and then stops driving this pin.
Input
The MSC8101 does not assume data bus ownership as long as it senses DBB is
asserted by an external bus master.
Input
Interrupt Request 3
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Input/Output
Data Bus Most Significant Word
In write transactions the bus master drives the valid data on this bus. In read
transactions the slave drives the valid data on this bus. In Host Port Disabled
mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode,
these bits are used as the bus in 32-bit mode.
Input/Output
Data Bus Bits 32–47
In write transactions the bus master drives the valid data on this bus. In read
transactions the slave drives the valid data on this bus.
Input/Output
Host Data
When the HDI16 interface is enabled, these signals are lines 0-15 of the
bidirectional tri-state data bus.
Input/Output
Data Bus Bits 48–51
In write transactions the bus master drives the valid data on these pins. In read
transactions the slave drives the valid data on these pins.
Input
Host Address Line 0–3
When the HDI16 interface bus is enabled, these lines address internal host
registers.
Description
2
1
1
2
3
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