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Table 2-12. External Configuration Signals
Pin
Description
RSTCONF
Reset Configuration
Input line sampled by the MSC8101 at the rising
edge of PORESET.
DBREQ/
EONCE Event Bit 0
EE0
Input line sampled after SC140 core PLL locks.
Holding EE0 high when PORESET is deasserted
puts the SC140 core into Debug mode.
HPE/EE1
Host Port Enable
Input line sampled at the rising edge of PORESET.
If asserted, the Host port is enabled, the system
data bus is 32-bit wide, and the Host must
program the reset configuration word.
BTM[0–1]/
Boot Mode
EE[4–5]
Input lines sampled at the rising edge of
PORESET, which determine the MSC8101 Boot
mode.
No.
Characteristics
1
Required external PORESET duration minimum
•
CLKIN = 18 MHz
•
CLKIN = 75 MHz
2
Delay from deassertion of external PORESET to
deassertion of internal PORESET
•
CLKIN = 18 MHz
•
CLKIN = 75 MHz
3
Delay from deassertion of internal PORESET to SPLL lock
•
SPLLMFCLK = 18 MHz
•
SPLLMFCLK = 25 MHz
4
Delay from SPLL lock to DLL lock
•
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
•
DLL disabled
5
Delay from SPLL lock to HRESET deassertion
•
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
•
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
6
Delay from SPLL lock to SRESET deassertion
•
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
•
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
Note:
Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.
0
Reset Configuration Master.
1
Reset Configuration Slave.
0
SC140 core starts the normal processing
mode after reset.
1
SC140 core enters Debug mode immediately
after reset.
0
Host port disabled (hardware reset
configuration enabled).
1
Host port enabled.
00
MSC8101 boots from external memory.
01
MSC8101 boots from HDI16.
10
Reserved.
11
Reserved.
Table 2-13. Reset Timing
Expression
16 / CLKIN
1024 / CLKIN
800 / SPLLMFCLK
3073 / BLCK
3585 / BLCK
512 / BLCK
3588 / BLCK
515 / BLCK
AC Timings
Settings
Min
Max
888.8
—
213.3
—
56.89
13.65
44.4
32.0
170.72
40.97
—
0.0
199.17
47.5
28.4
6.83
199.33
47.84
28.61
6.87
Unit
ns
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
µs
µs
µs
2-9
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