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Table 1-3. Reset, Configuration, and EOnCE Event Signals (Continued)
Signal Name
Type
BTM[0–1]
Input
Boot Mode 0–1
Determines the MSC8101 boot mode when PORESET is deasserted. See the Emulation
and Debug chapter in the SC140 DSP Core Reference Manual for details on how to set
these pins.
1
EE4
EOnCE Event 4
After PORESET is deasserted, you can configure EE4 as an input (default) or an output.
See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for
details on the ETRSMT Register.
Input
Enable Address Event Detection Channel 4 or generate one of the EOnCE events
Output
EOnCE Transmit Register (ETRSMT) was written by the DSP. Used to trigger external
debugging equipment.
1
EE5
EOnCE Event 5
After PORESET is deasserted, you can configure EE5 as an input (default) or an output.
Input
Enable Address Event Detection Channel 5.
Output
Detection by Address Event Detection Channel 5. Used to trigger external debugging
equipment.
1
EED
Enhanced OnCE (EOnCE) Event Detection
After PORESET is deasserted, you can configure EED as an input (default) or output:
Input
Enable the Data Event Detection Channel.
Output
Detection by the Data Event Detection Channel. Used to trigger external debugging
equipment.
PORESET
Input
Power-On Reset
When asserted, this line causes the MSC8101 to enter power-on reset state.
RSTCONF
Input
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function
is provided in the "Power-On Reset Flow" and "Hardware Reset Configuration" sections of
the MSC8101 Reference Manual .
HRESET
Input
Hard Reset
When asserted, this open-drain line causes the MSC8101 to enter hard reset state.
SRESET
Input
Soft Reset
When asserted, this open-drain line causes the MSC8101 to enter soft reset state.
Note:
See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on how to
configure these pins.
Reset, Configuration, and EOnCE Event Signals
Signal Description
1-7
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