Table of Contents
Advertisement
Name
General-
Peripheral Controller:
Purpose
Dedicated Signal
I/O
Protocol
PA26
FCC1: RXCLAV
UTOPIA slave
FCC1: RXCLAV
UTOPIA master, or
RXCLAV0
UTOPIA master, Multi-PHY,
direct polling
FCC1: RX_ER
MII
PA25
FCC1: TXD0
UTOPIA
SDMA: MSNUM0
PA24
FCC1: TXD1
UTOPIA
SDMA: MSNUM1
PA23
FCC1: TXD2
UTOPIA
Communications Processor Module (CPM) Ports
Table 1-3. Port A Signals (Continued)
Dedicated
I/O Data
Direction
Output
FCC1: UTOPIA Slave Receive Cell Available
In the ATM UTOPIA interface supported by FCC1. RXCLAV
is asserted by the MSC8101 (UTOPIA slave PHY) when
one complete ATM cell is available for transfer.
Input
FCC1: UTOPIA Master Receive Cell Available
In the ATM UTOPIA interface supported by FCC1. RXCLAV
is asserted by an external PHY when one complete ATM
cell is available for transfer.
Input
FCC1: UTOPIA Master Receive Cell Available 0 Direct
Polling
In the ATM UTOPIA interface supported by FCC1,
RXCLAV0 is asserted by an external PHY when one
complete ATM cell is available for transfer.
Input
FCC1: Media Independent Interface Receive Error
In the MII interface and supported by FCC1. RX_ER is
asserted by an external fast Ethernet PHY. This signal
indicates a receive error, which often indicates bad wiring.
Output
FCC1: UTOPIA Transmit Data Bit 0
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 outputs ATM cell octets (UTOPIA interface data)
on TXD[0–7]. TXD7 is the most significant bit. TXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes.
Output
Module Serial Number Bit 0
MSNUM[0–4] of is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates
which section, transmit (0) or receive (1), is active during
the transfer.
Output
FCC1: UTOPIA Transmit Data Bit 1
In the ATM UTOPIA interface supported by FCC1. The
MSC8101 outputs ATM cell octets (UTOPIA interface data)
on TXD[0–7]. TXD7 is the most significant bit. TXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes.
Output
Module Serial Number Bit 1
MSNUM[0–4] of is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates
which section, transmit (0) or receive (1), is active during
the transfer.
Output
FCC1: UTOPIA Transmit Data Bit 2
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8101 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Description
1-21
Advertisement
Table of Contents
