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Clock Configuration
COREPDF
COREMF
SPLLPDF
SPLLMF
2-6
Defaults
Name
Bit No.
Hard
PORESET
Reset
—
—
—
0–1
Configuration
Unaffected Core PLL Pre-Division Factor
2–3
Pins
Configuration
Unaffected Core Multiplication Factor
4–7
Pins
BUSDF
Configuration
Unaffected 60x Bus Division Factor
8–11
Pins
CPMDF
Configuration
Unaffected CPM Division Factor
12–15
Pins
Configuration
Unaffected SPLL Pre-Division Factor
16–19
Pins
Configuration
Unaffected SPLL Multiplication Factor
20–23
Pins
—
—
—
24
DLLDIS
Configuration
Unaffected DLL Disable
25
Pins
—
—
—
26–31
Table 2-8. SCMR Bit Descriptions
Description
Reserved
Reserved
Reserved
Settings
00
CPLL PDF= 1
01
CPLL PDF= 2
10
CPLL PDF= 3
11
CPLL PDF= 4
0101
MF = 10
0110
MF = 12
All other combinations not used.
0010
Bus DF = 3
0011
Bus DF = 4
0100
Bus DF = 5
All other combinations not used.
0001 CPM DF = 2
All other combinations are not
used.
0000
SPLL PDF = 1
0001
SPLL PDF = 2
0010
SPLL PDF = 3
0011
SPLL PDF = 4
All other combinations not used
0110
SPLL MF = 12
0111
SPLL MF = 14
1000
SPLL MF = 16
1001
SPLL MF = 18
1010
SPLL MF = 20
1011
SPLL MF = 22
1100
SPLL MF = 24
1101
SPLL MF = 26
1110
SPLL MF = 28
1111
SPLL MF = 30
All other combinations not used
0
DLL operation is enabled
1
DLL is disabled
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