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FCC1
ATM/UTOPIA
FCC1
MPHY
MPHY
Master
HDLC/
Master
Ethernet
mux poll
transp.
dir. poll
MII
or Slave
Serial
TXENB
COL
TXCLAV
TXCLAV0
CRS
RTS
TXSOC
TX_ER
RXENB
TX_EN
RXSOC
RX_DV
RXCLAV
RXCLAV0
RX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
TXD3
TXD5
TXD2
TXD6
TXD1
TXD7
TXD0
TXD
RXD7
RXD0
RXD
RXD6
RXD1
RXD5
RXD2
RXD4
RXD3
RXD3
RXD2
RXD1
RXD0
FCC2
HDLC/
Ethernet
transp.
MII
Serial
TX_ER
RX_DV
TX_EN
RX_ER
RTS
COL
CRS
TXD3
TXD2
TXD1
TXD0
TXD
RXD0
RXD
RXD1
RXD2
RXD3
TXADDR0
RXADDR0
TXADDR1
RXADDR1
FCC1
TXADDR2/
TXADDR2
CTS
TXCLAV1
RXADDR2/
RXADDR2
CD
RXCLAV1
FCC2
CTS
CD
RXADDR3 RXCLAV2
TXADDR4
TXCLAV3
RXADDR4 RXCLAV3
RXPRTY
TXPRTY
TXADDR3
TXCLAV2
HDLC
Nibble
TXD3
TXD2
TXD1
TXD0
RXD0
RXD1
RXD2
RXD3
SMC2
SMTXD
SMRXD
HDLC
SMSYN
Nibble
SCC2
RXD
TXD
RTS/TENA
TXD3
TXD2
TXD1
TXD0
RXD0
RXD1
RXD2
RXD3
Ext. Req.
EXT1
SCC1
CTS/CLSN
CTS/CLSN
Ext. Req.
EXT2
SCC1
SMTXD
CTS/CLSN
CD/RENA
CTS/CLSN
CD/RENA
SMC1
SMTXD
SMRXD
RXD
TXD
RTS/TENA
SMSYN
Figure 1-2. CPM Port A–D Pin Multiplexed Functionality
SI1
TDMA1
Serial
Nibble
L1TXD
L1TXD0
L1RXD
L1RXD0
L1TSYNC
SI2
L1RSYNC
TDMB2
L1TXD
L1RXD
L1RSYNC
L1TSYNC
TDMC2
L1TXD
L1RXD
L1TXD3
L1TSYNC
L1RXD3
L1RSYNC
TDMD2
L1RXD2
L1TXD
L1RXD1
L1RXD
L1TXD2
L1TSYNC
L1TXD1
L1RSYNC
LIST1
LIST2
LIST4
LIST3
LIST1
LIST2
LIST3
LIST4
Signal Groupings
SDMA
MSNUM0
MSNUM1
MSNUM2
MSNUM3
MSNUM4
MSNUM5
2
I
C
SDA
SCL
BRGs Clocks Timers
BRG1O
CLK1 TGATE1 PC31
BRG2O
CLK2
TOUT1
BRG3O
CLK3
TIN2
TIN1/
SIU Timer Input
BRG4O
CLK4
TOUT2
CLK5
BRG5O
CLK5 TGATE2 PC27
TMCLK
BRG6O
CLK6
TOUT3
DMA
BRG7O
CLK7
TIN4
DACK2
TIN3/
DREQ2
BRG8O
CLK8
TOUT4
DACK1
CLK9
DREQ1
CLK10
DRACK1/DONE1
DRACK2/DONE2
SPI
BRG1O
SPISEL
SPICLK
SPIMOSI
BRG2O
SPIMISO
GPIO
PA31
PA30
PA29
PA28
PA27
PA26
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PB31
PB30
PB29
PB28
PB27
PB26
PB25
PB24
PB23
PB22
PB21
PB20
PB19
PB18
PC30
PC29
PC28
PC26
PC25
PC24
PC23
PC22
PC15
PC14
PC13
PC12
PC7
PC6
PC5
PC4
PD31
PD30
PD29
PD19
PD18
PD17
PD16
PD7
1-3
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