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Name
General-
Peripheral Controller:
Purpose
Dedicated I/O
I/O
Protocol
PB20
FCC2: RXD1
MII and HDLC nibble
SI1 TDMA1: L1TXD1
TDM nibble
SI2 TDMD2: L1RSYNC
TDM serial
PB19
FCC2: RXD2
MII and HDLC nibble
2
I
C: SDA
PB18
FCC2: RXD3
MII and HDLC nibble
2
I
C: SCL
Communications Processor Module (CPM) Ports
Table 1-4. Port B Signals (Continued)
Dedicated
I/O Data
Direction
Input
FCC2: MII and HDLC Nibble: Receive Data Bit 1
RXD[0–3] is supported by MII and HDLC nibble mode in
FCC2. RXD3 is the most significant bit. RXD0 is the least
significant bit.
Output
Time-Division Multiplexing A1: Nibble Layer 1 Transmit
Data Bit 1
In the TDMA1 interface supported by SI1. TDMA1 supports
bit and nibble modes. L1TXD3 is the most significant bit.
L1TXD0 is the least significant bit in nibble mode. TDMA1
transmits nibble data out of L1TXD[0–3].
Input
Time-Division Multiplexing D2: Layer 1 Receive
Synchronize Data
In the TDMD2 interface supported by SI2, this is the
synchronizing signal for the receive channel.
Input
FCC2: MII and HDLC Nibble Receive Data Bit 2
RXD[0–3] is supported by MII and HDLC nibble mode in
FCC2. RXD3 is the most significant bit. RXD0 is the least
significant bit.
2
Input/
I
C: Inter-Integrated Circuit Serial Data
2
Output
The I
C interface comprises two signals: serial data (SDA)
and serial clock (SDA). The I
synchronous, multimaster bus that can connect several
integrated circuits on a board. Clock rates run up to
520 kHz@25 MHz system clock.
Input
FCC2: MII and HDLC Nibble Receive Data Bit 3
RXD[0–3] is supported by MII and HDLC nibble mode in
FCC2. RXD3 is the most significant bit. RXD0 is the least
significant bit.
2
Input/
I
C: Inter-Integrated Circuit Serial Clock
2
Output
The I
C interface comprises two signals: serial data (SDA)
and serial clock (SDA). The I
synchronous, multimaster bus that can connect several
integrated circuits on a board. Clock rates run up to
520 kHz@25 MHz system clock.
Description
2
C controller uses a
2
C controller uses a
1-31
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