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2.6.2.1 System Clock Control Register
Bit 0
1
2
3
TYPE
RESET
16
17
18
19
TYPE
RESET
Figure 2-1. System Clock Control Register (SCCR)—0x10C80
The SCCR is memory-mapped into the SIU register map of the MSC8101.
Defaults
Name
Hard
Bit No.
PORESET
Reset
—
—
0–29
DFBRG
01
Unaffected Division Factor for the BRG Clock
30–31
2.6.2.2 System Clock Mode Register
Bit 0
1
2
3
—
COREPDF
TYPE
RESET
16
17
18
19
SPLLPDF
TYPE
RESET
Figure 2-2. System Clock Mode Register (SCMR)—0x10C88
SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode
control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined
configuration settings. For details of the available setting options, see AN2288.
4
5
6
7
—
R/W
—
20
21
22
23
24
—
R/W
—
Table 2-7. SCCR Bit Descriptions
Description
—
Reserved
Defines the BRGCLK frequency. Changing
this value does not result in a loss of lock
condition.
4
5
6
7
8
COREMF
R
—
20
21
22
23
24
SPLLMF
—
R
—
Clock Configuration
8
9
10
11
12
25
26
27
28
Settings
00
Divide by 4
01
Divide by 16 (default value)
10
Divide by 64
11
Divide by 256
9
10
11
12
BUSDF
25
26
27
28
DLLDIS
—
13
14
15
29
30
31
DFBRG
13
14
15
CPMDF
29
30
31
2-5
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