Msc8101 Features - Motorola Digital DNA MSC8101 Technical Data Manual

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MSC8101 Features

• SC140 Core
• 150 MHz Communications Processor Module (CPM)
• 100 MHz 64- or 32-bit Wide Bus Interface
• Enhanced Filter Coprocessor (EFCOP)
• Programmable Memory Controller
• Large On-Chip SRAM
• DMA Controller
• Small Foot Print Package
• Very Low Power Consumption
• Enhanced 16-bit Parallel Host Interface (HDI16)
• Phase-Lock Loops (PLLs)
• Process Technology
— Architecture optimized for efficient C/C++ code compilation
— Four 16-bit ALUs and two 32-bit AGUs
— 1200 DSP MIPS, 1200 MMACS, 3000 RISC MIPS, running at 300 MHz
— Very low power dissipation—less than 0.25 W for the core running full speed at 1.6 V
— Variable-Length Execution Set (VLES) execution model
— JTAG/Enhanced OnCE debug port
— Programmable protocol machine using a 32-bit RISC engine
— 155 Mbps ATM interface (including AAL 0/1/2/5)
— 10/100 Mbit Ethernet interface
— Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
— HDLC support up to T3 rates, or 256 channels
— Support for bursts for high efficiency
— Glueless interface to 60x-compatible bus systems
— Multi-master support
— Independently and concurrently executes long filters (such as echo cancellation)
— Runs at 300 MHz and provides 300 MMACS performance
— Control for up to eight banks of external memory
— User-programmable machines (UPM) allowing glueless interface to various memory types
(SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals
— Dedicated pipelined SDRAM memory interface
— 256K 16-bit words (512 KB)
— Unified program and data space configurable by the application
— Word and byte addressable
— 16 DMA channels, FIFO based, with burst capabilities
— Sophisticated addressing capabilities
— 17 mm × 17 mm plastic package
— Estimated power consumption of 570 mW for the entire device
— Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
— Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
— System PLL
— CPM DPLLs (SCC and SCM)
— Uses 0.13 micron copper interconnect process technology
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