Electrical Design Considerations; Power Considerations - Motorola Digital DNA MSC8101 Technical Data Manual

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Electrical Design Considerations

4.2 Electrical Design Considerations
The input voltage must not exceed the I/O supply
power-on reset. In turn,
no more than 100 ms.
V
DD
Therefore the recommendation is to use "bootstrap" diodes between the power rails, as shown in Figure
4-1..
Select the bootstrap diodes such that a nominal V
until the
diodes are connected in series; each has a forward voltage (V
provide a 2.4 V drop, maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply
stabilizes at 1.6 V, the bootstrap diodes will be reverse biased with negligible leakage current. The V
should be effective at the current levels required by the processor. Do not use diodes with a nominal V
that drops too low at high current.

4.3 Power Considerations

The internal power dissipation consists of three components:
The power dissipation depends on the operating frequency of the different portions of the chip. The
numbers given in Table 4-1 refer to 300 MHz core frequency, 150 MHz CPM frequency, and 100 MHz
SIU frequency.
To determine the power dissipation at a given frequency, the following equations should be applied:
To determine a total power dissipation in a specific application, the following equation should be applied
for each I/O output pin:
Equation 2: P = C × V
Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz.
4-2
can exceed
V
DDH
should not exceed
V
DDH
/
must not exceed
V
V
CCSYN
DDH
I/O Power
Core/PLL
Supply
Figure 4-1. Bootstrap Diodes for Power-Up Sequencing
V
/
V
power supply becomes active. In Figure 4-1., four MUR420 Schottky barrier
DD
CCSYN
P
= P
+ P
+ P
INT
CORE
SIU
CPM
)/300) × f + P
P
(f) = ((P
– P
CORE
CORE
LCO
)/100) × f + P
P
(f) = ((P
– P
SIU
SIU
LSI
)/150) × f + P
P
(f) = ((P
– P
CPM
CPM
LCP
Where f is the operating frequency in MHz and all power numbers are in mW.
2
× f × 10
–3
DDH
by more than 2.5 V at any time, including during
V
DDH
/
by more than 3.3 V during power-on reset, but for
V
V
DD
CCSYN
/
by more than 2.1 V during normal operation.
V
V
DD
CCSYN
by more than 0.4 V at any time, including during power-on reset.
MUR420
MUR420
MUR420
MUR420
/V
is sourced from the
DD
CCSYN
) of 0.6 V at high currents, so these diodes
F
LCO
LSI
LCP
3.3 V (V
)
DDH
1.6 V (V
/V
)
DD
CCSYN
power supply
V
DDH
F
F

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