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Signal Groupings
For the signals
multiplexed on
Ports A–D,
see Figure 1-2
EOnCE Event
EED
EE0
EE1
EE[2–3]
EE[4–5]
BNKSEL[0–2]
TC[0–2]
Note:
Refer to the System Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to configure these pins.
1-2
→ 14
VDD
→ 25
VDDH
P
→
VCCSYN
1
O
→
VCCSYN1
1
W
E
→ 37
GND
R
→
GNDSYN
1
→
GNDSYN1
1
C
P
Port A
↔ 26
M
PA[31–6]
I
Port B
/
↔ 14
PB[31–18]
O
Port C
P
↔ 18
PC[31–22, 15–12, 7–4]
O
R
Port D
T
↔
PD[31–29, 19–16, 7]
8
S
→
TMS
1
J
→
TDI
1
T
→
TCK
1
A
→
TRST
1
G
←
TDO
1
RESET
Configuration
↔
1
↔
DBREQ
1
↔
HPE
1
↔
2
↔
BTM[0–1]
2
→
PORESET
1
→
RSTCONF
1
↔
HRESET
1
↔
SRESET
1
→
CLKIN
1
→
MODCK[1–3]
3
←
CLKOUT
1
→
DLLIN
1
→
TEST
1
↔
THERM[1–2]
2
↔
SPARE1, SPARE5
2
Figure 1-1. MSC8101 External Signals
↔ A[0–31]
32
↔ TT[0–4]
5
↔ TSIZ[0–3]
4
↔ TBST
1
↔ IRQ1
GBL
1
→ Reserved
BADDR[29–31]
3
↔ BR
1
↔ BG
1
↔ ABB
IRQ2
1
↔ TS
1
↔ AACK
1
← ARTRY
1
↔ DBG
1
↔ DBB
IRQ3
1
↔ D[0–31]
32
↔ D[32–47]
HD[0–15]
16
↔ D[48–51]
4
HA[0–3]
↔ D52
HCS1
1
Single DS
6
↔ D53
HRW
1
0
↔ D54
HDS/HDS
x
1
Single HR
B
↔ D55
HREQ/HREQ
1
U
↔ D56
1
HACK/HACK
S
↔ D57
HDSP
1
↔ D58
HDDS
1
↔ D59
1
H8BIT
↔ D60
HCS2
1
↔ D[61–63]
Reserved
4
← Reserved
DP0
1
↔ IRQ1
DP1
1
↔ IRQ2
DP2
1
↔ IRQ3
1
DP3
↔ IRQ4
DP4
1
↔ IRQ5
DP5
1
↔ IRQ6
DP6
1
↔ IRQ7
DP7
1
↔ TA
1
↔ TEA
1
← NMI
1
→ NMI_OUT
1
↔ PSDVAL
1
↔ IRQ7
1
INT_OUT
→ CS[0–7]
8
→ BCTL1
1
→ BADDR[27–28]
2
→ ALE
1
→ BCTL0
M
1
E
→ PWE[0–7]
8
PSDDQM[0–7]
M
→ PSDA10
1
C
→ PSDWE
1
→ POE
1
→ PSDCAS
1
↔ PGTA
1
PUPMWAIT
→ PSDAMUX
1
IRQ[2–3, 5]
HDI16 Signals
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
Reserved
EXT_Br2
IRQ1
EXT_BG2
Reserved
EXT_DBG2
Reserved
EXT_BR3
DREQ3
EXT_BG3
DREQ4
EXT_DBG3
DACK3
IRQ6
DACK4
IRQ7
PBS[0–7]
PGPL0
PGPL1
PSDRAS
PGPL2
PGPL3
PPBS
PGPL4
PGPL5
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