REFCLK
AACK/ARTRY/TA/TEA/DBG/BG/BR
DATA bus
DP input
All other inputs
PSDVAL/TEA/TA
Address bus/Address attributes/GBL
BADDR
Data bus
DP output
Memory controller/ALE
All other outputs
Figure 2-6. Bus Signals
10
11
10
12
10
14
10
15
31
32a
32b
33a
33b
34
35
AC Timings
2-13