Motorola Digital DNA MSC8101 Technical Data Manual page 64

AC Timings
2.7.3.2 DMA Data Transfers
Table 2-17 describes the DMA signal timing.
Number
The DREQ
edge of
the timings in Table 2-17. Figure 2-7 shows synchronous peripheral interaction.
2.7.4 HDI16 Signals
Number
2-14
72 DREQ setup time before REFCLK falling edge
73 DREQ hold time after REFCLK falling edge
74 DONE setup time before REFCLK rising edge
75 DONE hold time after REFCLK rising edge
76 DACK/DRACK/DONE delay after REFCLK rising edge
signal is synchronized with the falling edge of
. To achieve fast response, a synchronized peripheral should assert
REFCLK
DACK/DONE/DRACK Outputs
Table 2-18. Host Interface (HDI16) Timing
Characteristics
44a Read data strobe assertion width
HACK read assertion width
44b Read data strobe deassertion width
HACK read deassertion width
44c Read data strobe deassertion width
5,6
Register" reads , or between two consecutive CVR, ICR,
7
or ISR reads
HACK deassertion width after "Last Data Register" reads
45 Write data strobe assertion width
HACK write assertion width
46 Write data strobe deassertion width
HACK write deassertion width after ICR, CVR and Data
5
Register writes
Table 2-17. DMA Signals
Characteristic
REFCLK
REFCLK
DREQ
74
DONE Input
Figure 2-7. DMA Signals
3
4
4
4
after "Last Data
5,6
8
8
Minimum Maximum
6 —
0.5 —
9 —
0.5 —
0.5 9
. DONE timing is relative to the rising
according to
DREQ
73
72
75
76
1, 2
Expression Min Max
T + 3.3 6.6 —
C
T + 3.3 6.6 —
C
(2.5 × T
) + 3.3 11.6 —
C
T + 3.3 6.6 —
C
(2.5 × T
) + 3.3 11.6 —
C
Units
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns