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AC Timings
2.7.2.3 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after
PORESET
signals described in Table 2-12 one the rising edge of
If HPE is sampled high, the host port is enabled. In this mode the
device extends the internal
host must write four 8-bit half-words to the Host Reset Configuration Register address to program the
reset configuration word, which is 32 bits wide. For more information, see the MSC8101 Reference
Manual. The reset configuration word is programmed before the internal PLL and DLL in the MSC8101
are locked. The host must program it after the rising edge of the
must have its own clock that does not depend on the MSC8101 clock. After the PLL and DLL are locked,
HRESET
bus clocks later (see Figure 2-3).
2.7.2.4 Hardware Reset Configuration
Hardware reset configuration is enabled if HPE is sampled low at the rising edge of
driven on
configuration. If
configuration slave. If
as a configuration master. Section 2.7.2.4, Hardware Reset Configuration, explains the configuration
sequence and the terms "configuration master" and "configuration slave."
Directly after the deassertion of
master or configuration slave, the MSC8101 starts the configuration process. The MSC8101 asserts
HRESET
takes 1024
mode.
2-10
is deasserted, as described in the MSC8101 Reference Manual. The MSC8101 samples the
PORESET
remains asserted for another 512 bus clocks and is then released. The
1
PORESET
RSTCONF, HPE
Input
asserted for
HRM, BTM
min 16
pins are sampled
CLKIN.
PORESET
Internal
Any time
HRESET
Output (I/O)
SRESET
Output (I/O)
Figure 2-3. Host Reset Configuration Timing
while
RSTCONF
PORESET
is deasserted (driven high) while
RSTCONF
RSTCONF
and
throughout the power-on reset process, including configuration. Configuration
SRESET
CLOCKIN
cycles, after which
PORESET
until the host programs the reset configuration word register. The
MODCK[1–3] pins
are sampled.
Host programs
MODCK_H bits
Reset Configuration
are ready for PLL.
Word
PLL locked
3
2
PLL locks after
800 SPLLMFCLKs and
DLL locks 3073 BUS clocks
after PLL is locked.
When DLL is disabled,
reset period is shortened by
DLL lock time.
changes from assertion to deassertion determines the MSC8101
is asserted (driven low) while
and choice of the reset operation mode as configuration
PORESET
MODCK[1–3]
are sampled to determine the MSC8101's working
when the signal is deasserted.
pin must be pulled up. The
RSTCONF
input. In this mode, the host
PORESET
is released three
SRESET
DLL locked
4
5
6
HRESET/SRESET are
extended for 512/515 BUS
clocks, respectively, from PLL
and DLL lock
PORESET
changes, the MSC8101 acts as a
PORESET
PORESET
changes, the MSC8101 acts
. The value
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