Table of Contents
Advertisement
4.1 Line Interface
The line interface is used to connect an optical transceiver or receiver on the line side.
The following figure is an outline block diagram of the line interface of the µPD98413. The transmit/receive clock
paths can be changed by setting pins and registers. This block consists of parallel-to-serial (MUX), serial-to-parallel
(DEMUX), TxPLL, and clock and data recovery unit (CDR).
BIASP
RFCKTTL
RFCKPLT/
RFCKPLC
TDOT0/
TDOC0
RDIT0/
RDIC0
CD0
CDVREF
LPFCGND0
CHAPTER 4 INTERFACES
CHAPTER 4 INTERFACES
Figure 4-1. Overview of µ µ µ µ PD98413 line interface block
LPFP
LPFPGND
TxPLL
Lock state
CDR
CD
CNT
LPFC0
BIASC0
MUX 0
8:1
DEMUX 0
1:8
PRELIMINARY
78MHz
FRAMER0
78MHz
2
1
PORT 0
NEC confidential and Proprietary
3
111
Advertisement
Table of Contents
