Internal Configuration Of Boundary Scan Circuit - NEC UPD98413 User Manual

CHAPTER 6 JTAG BOUNDARY SCAN

6.2 Internal Configuration of Boundary Scan Circuit

Figure 6-1 shows the block diagram of the internal JTAG boundary scan circuit of the µPD98413.
Figure 6-1. Block Diagram of Boundary Scan Circuit
Boundary scan register
Bypass register
Output buffer
JDO
MUX
JDI
Instruction decoder
Instruction register
JMS
TAP
controller
JCK
JRST_B
6.2.1 Instruction Register
The instruction register consists of a two-bit shift register and writes instruction data from the JDI pin. The register
and instruction are selected by this instruction data.
6.2.2 TAP (Test Access Port) Controller
The TAP controller changes operating state by latching the signal of the JMS pin at the rising edge of the clock input
to the JCK pin.
6.2.3 Bypass Register
The bypass register consists of a one-bit shift register connected between the JDI and JDO pins when the TAP
controller is in Shift-DR state. If this register is selected while the TAP controller is in Shift-DR state, data is shifted to
the JDO pin at the rising edge of the clock input to the JCK pin.
When this register is selected, the operation of the JTAG boundary circuit does not influence on the operation of the
µPD98413.
6.2.4 Boundary Scan Register
The boundary scan register is located between an external pin of the mPD98414 and internal logic circuit. When this
register is selected, data is latched or loaded by the instruction of the TAP controller.
If this register is selected while the TAP controller is in Shift-DR state, data is output to the JDO pin starting from the
LSB at the falling edge of the clock input to the JCK pin.
306
PRELIMINARY
NEC confidential and Proprietary