NEC UPD98413 User Manual page 20

Pin Name Serial No.
TXCLK
TXDATA[31:0]
TXSOC
TXENB_B
TXCLAV0-3
TXPRTY
TXADDR[1:0]
20
CHAPTER 2 PIN FUNCTION
Address No. I/O Level
I
LVTTL
I
LVTTL
I
LVTTL
I
LVTTL
O
LVTTL
I
LVTTL
(Internal
pull-up)
I
LVTTL
PRELIMINARY
Function
Transmit clock input.
This pin inputs the clock, up to 104 MHz, used to transfer
transmit data.
Transmit data input bus.
These pins form a 32-bit data bus through which transmits
cell data is input. The µPD98413 samples the data on this
bus at the rising edge of TXCLK.
Transmit start of cell input.
This pin is inputted a signal that indicates the start position
µ
of a transmit cell. The PD98413 recognizes the clock cycle
in which TXSOC is high as the first word of a cell.
Transmit enable signal input.
This signal indicates that the ATM device has output valid
transmit cell data to TXDATA. The
TXENB_B at the rising edge of TXCLK. If TXENB_B is low,
it loads the data on TXSOC and TXDATA to the transmit
FIFO at the edge of TXCLK. If TXENB_B is high, the data
on TXSOC and TXDATA is not loaded to the transmit FIFO.
Transmit cell buffer available.
This signal posts notification of the vacancy of the transmit
FIFO to the ATM device. If the number of cells stored in the
transmit FIFO has reached the threshold value set by the
APHIGH[7:0] bits of the FTHT1 register, the
drives TXCLAV low. The subsequent cells are dropped and
the µPD98413 reports an overflow of the transmit FIFO.
TXCLAV0 corresponds to PORT0, while TXCLAV3
corresponds to PORT3.
Transmit data path parity.
This pin inputs the odd parity bit of the data input to
µ
TXDATA. The PD98413 calculates parity based on the
input data and parity bit. If it detects an error, it sets the
PARE bit of the APIET register to report the error. An even
parity can be also used depending on the setting of the
MDAPIT register.
Transmit address input.
These pins are used to input a port address for data
transmission.
NEC confidential and Proprietary
(2/2)
µ
PD98413 samples
µ
PD98413