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CHAPTER 6 JTAG BOUNDARY SCAN
(9) Exit2-DR
This is a temporary controller state. If the JMS pin signal is held high at the rising edge of the JCK pin signal with the
TAP controller in this state, the controller enters the Update-DR state. This ends the scan process.
If the JMS pin signal is held low at the rising edge of the JCK pin signal, the TAP controller enters the Shift-DR state.
Both the bypass register and boundary scan register selected by the current instruction hold the previous status
without change. While the TAP controller is in this state, the instruction does not change.
(10) Update-DR
The boundary scan register has a parallel output latch to prevent changes in parallel output (while shifted to the shift
register path concatenated) by certain instructions (for example, EXTEST instruction).
In the Update-DR controller state, data is latched from the shift register to the parallel output latch of this register at
the falling edge of the JCK pin signal.
The data retained latched to the parallel output latch changes depending on this controller state (the data does not
change with the other controller states).
The previous states of all the shift register of the boundary scan register selected by the current instruction are
retained.
While the TAP controller is in this state, the instruction does not change.
If the JMS pin signal is held high at the rising edge of the JCK pin signal with the TAP controller in this state, the
controller enters the Select-DR-Scan state.
If the JMS signal is held low at the rising edge of the JCK pin signal, the TAP controller enters the Run-Test/Idle state.
(11) Capture-IR
In this controller state, the shift register loads the pattern of a fixed logic value [01 (binary)] to the instruction register
at the rising edge of the JCK pin signal.
The previous states of both the bypass register and boundary scan register selected by the current instruction are
retained without change.
While the TAP controller is in this state, the instruction does not change.
If the JMS pin signal is held high at the rising edge of the JCK pin signal while the controller is in this state, the
controller enters the Exit1-IR state.
If the JMS pin signal is held low at the rising edge of the JCK pin signal, the TAP controller enters the Shift-IR state.
(12) Shift-IR
In this controller state, JDI and JDO are connected by the shift register in the instruction register. The shift data is
shift one state toward the serial output direction at each rising edge of the JCK pin signal.
The boundary scan register or bypass register selected by the current instruction holds the previous state without
change.
While the TAP controller is in this state, the instruction does not change.
If the JMS pin signal is held high at the rising edge of the JCK pin signal with the TAP controller in this state, the
controller enters the Exit1-IR state. If the JMS pin signal is held low, the controller remains the Shift-IR state.
311
PRELIMINARY
NEC confidential and Proprietary
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