NEC UPD98413 User Manual page 308

JCK
Controller state
(1) Test-Logic-Reset
The JTAG boundary scan circuit performs no operation on the mPD98414. Therefore, it does not affect the system
logic of the mPD98414. This is because the bypass instruction is stored to the instruction register and executed on
initialization. The TAP controller enters the Test-Logic-Reset state if the JMS pin signal holds the high level for the
duration of at least five rising edges of the JCK pin signal, regardless of the current state of the controller. The TAP
controller holds this state for the duration in which the JMS pin signal high.
If the TAP controller must be in the Test-Logic-Reset state, the controller returns to the original Test-Logic-Reset
state even if a low-level signal is input once to the JMS pin by mistake (due to, for example, the influence of the
external interface), if the JMS pin signal holds its high level status for the duration of three rising edges of the JCK pin
signal.
The operation of the test logic does not hinder the logic operation of the mPD98414 due to the above error.
When the TAP controller exits from the Test-Logic-Reset state, the controller enters the Run-Test/Idle state. In this
state, no operation is performed because the current instruction is set by the operation of the bypass register. The
logic operation of the JTAG boundary scan circuit is inactive even in the Select-DR-Scan and Select-IR-Scan states.
(2) Run-Test/Idle
The TAP controller is in this state during scan operation (in Select-DR-Scan or Select-IR-Scan state). Once the
controller has entered this state and if the JMS pin signal holds the low level, the controller remains in this state.
The controller enters the Select-DR-Scan state if the JMS pin signal holds high level at one rising edge of the JCK pin
signal.
All the test data registers (boundary register and bypass register) selected by the current instruction hold the previous
status (Idle). While the TAP controller is in this state, the instruction does not change.
(3) Select-DR-Scan
This is a temporary boundary scan state. The boundary scan register and bypass register selected by the current
instruction hold the previous state.
If the JMS signal is held low at the rising edge of the JCK pin signal while the TAP controller is in this state, the
controller enters the Capture-DR state, and scan sequence to the selected registers is started.
If the JMS signal is held high at the rising edge of the JCK pin signal, the TAP controller enters the Select-IR-Scan
state. While the controller is in this state, the instruction does not change.
CHAPTER 6 JTAG BOUNDARY SCAN
Figure 6-3. Operation Timing in Controller State
Starts in state at rising edge of
Enters state
JCK pin
PRELIMINARY
Starts in state at rising edge
of JCK pin
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