Transmit Section And Line Dcc Insert Interface; Receive Section And Line Dcc Extract Interface - NEC UPD98413 User Manual

4.4.3 Transmit Section and Line DCC Insert Interface

TSDCLK is a 216kHz. TLDCLK is a 648kHz. TSD is sampled on the rising edge of TSDCLK. TLD is sampled
on the rising edge of TLDCLK. The D1-D3, and D4-D12 bytes shifted in to the µPD98413 in the frame shown are
inserted in the corresponding transport overhead channels in the next frame.
TSDCLK（O）
（216KHz）
b b b b
TSD（I）
TLDCLK（O）
（648KHz）
TLD（I）
b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b

4.4.4 Receive Section and Line DCC Extract Interface

RSDCLK is a 216kHz. RLDCLK is a 648kHz. RSD is updated on the falling edge of RSDCLK. RLD is updated
on the falling edge of RLDCLK. The D1-D3, and D4-D12 bytes shifted out of the µPD98413 in the frame shown
are extracted in the corresponding transport overhead channels in the previous frame.
RSDCLK（O）
（216KHz）
b b b b b
RSD（O）
RLDCLK（O）
（648KHz）
RLD（O）
b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b
144
CHAPTER 4 INTERFACES
Figure 4-23. DCC Insert timing
b b b b b
3×TSDCLK
Figure 4-24. DCC Extract timing
b b b b b
3×RSDCLK
PRELIMINARY
b b b b b b b b
b b b b b b b b
9×RLDCLK
b b b b b b b
b b b b b b b b b b b b b b b b b b b b b b b
9×TLDCLK
b b b b b b b b
b b b b b b b b b b b b b b b b b b b b b b b
NEC confidential and Proprietary
b b b
b