NEC UPD98413 User Manual page 277

(113) Receive counter sampling register (CSMPR)
This register specifies a command that saves the counter value of the performance monitoring counter to the
corresponding load register.
Register
Name
Port0:
CSMPR 02D8 H
31 30 29 28
15 14 13 12
Reserved
LPCR SPCR
Bit Field
D31-D14 Reserved Set to 0.
D13 LPCR 1: Loads the receive long packet counter. 0: Indicates completion of loading.
D12 SPCR 1: Loads the receive short packet counter. 0: Indicates completion of loading.
D11 FOPCR ATM mode:
1: Loads the receive FIFO overflow cell counter.
0: Indicates completion of loading.
POS mode:
1: Loads the receive FIFO overflow packet counter.
0: Indicates completion of loading.
D10 FEPCR ATM mode:
1: Loads the HEC error drop cell counter. 0: Indicates completion of loading.
POS mode:
1: Loads the receive FCS error packet counter. 0: Indicates completion of loading.
D9 AEPCR ATM mode:
1: Loads the HEC error correct cell counter. 0: Indicates completion of loading.
POS mode:
1: Loads the receive address error packet counter.
0: Indicates completion of loading.
D8 APCR ATM mode:
1: Loads the receive idle cell counter. 0: Indicates completion of loading.
POS mode:
1: Loads the receive abort packet counter. 0: Indicates completion of loading.
D7 VPCR ATM mode:
1: Loads the valid receive cell counter. 0: Indicates completion of loading.
POS mode:
1: Loads the valid receive packet counter. 0: Indicates completion of loading.
D6 NFJCR 1: Loads the Negative Frequency Justification counter
0: Indicates completion of loading.
D5 PFJCR 1: Loads the Positive Frequency Justification counter
0: Indicates completion of loading.
CHAPTER 5 REGISTERS
Address
Port1: Port2: Port3:
06D8 H 0AD8 H 0ED8 H
27 26 25 24
Reserved
11 10 9 8
FOPCR FEPCR AEPCR APCR
PRELIMINARY
Access Default
R/W 00000000 H
23 22 21 20
7 6 5 4
VPCR NFJCR PFJCR PREICR LREICR
Function
19 18 17 16
3 2 1 0
B3ECR B2ECR B1ECR
Default
0
0
0
0
0
0
0
0
NEC confidential and Proprietary
277