(59) Interrupt register (INT) Common register
The INT register indicates an interrupt occurrence of the lower cause.
Register
Address
Name
INT_RO
0140 H
31
30
29
28
15
14
13
12
Reserved
Bit
Field
Reserved
D31-
D12
GEV
D11
1: Indicates that the bits of the GEV register are set.
0: GEV register is all 0.
GPIN
D10
1: Indicates that the bits of the GPIN register are set.
0: GPIN register is all 0.
APIER
D9
1: Indicates that the ATM/POS interface errors occur.
0: APIER register is all 0.
D8
P3ICR
1: Indicates that the receive interrupt occurs in Port3.
0: Corresponding ICR register is all 0.
P2ICR
D7
1: Indicates that the receive interrupt occurs in Port2.
0: Corresponding ICR register is all 0.
D6
P1ICR
1: Indicates that the receive interrupt occurs in Port1.
0: Corresponding ICR register is all 0.
P0ICR
D5
1: Indicates that the receive interrupt occurs in Port0.
0: Corresponding ICR register is all 0.
D4
APIET
1: Indicates that the ATM/POS interface errors occur.
0: APIET register is all 0.
P3ICT
D3
1: Indicates that the transmit interrupt occurs in Port3.
0: Corresponding ICT register is all 0.
P2ICT
D2
1: Indicates that the transmit interrupt occurs in Port2.
0: Corresponding ICT register is all 0.
P1ICT
D1
1: Indicates that the transmit interrupt occurs in Port1.
0: Corresponding ICT register is all 0.
P0ICT
D0
1: Indicates that the transmit interrupt occurs in Port0.
0: Corresponding ICT register is all 0.
Note : Depends on the corresponding register status.
CHAPTER 5 REGISTERS
Access
Default
R
00000000 H
27
26
25
24
Reserved
11
10
9
8
GEV
GPIN
APIER
P3ICR
PRELIMINARY
Function
Read-only
23
22
21
20
7
6
5
4
P2ICR
P1ICR
P0ICR
APIET
Function
19
18
17
16
3
2
1
0
P3ICT
P2ICT
P1ICT
P0ICT
Default
All 0
0
0
0
0
0
0
0
0
0
0
0
0
NEC confidential and Proprietary
225